Hi Jury, There isn't a specific jitter requirement for DCLKIN. However, tPD will change based on the delay between the sample clock falling edge and the DCLKIN falling edge. Thus, the sample clock to DCLKIN relationship needs to remain consistent. Generating the DCLKIN from the FPGA should be okay as long as it's through a PLL that locks to the sample clock phase. Best regards, Drew
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Forum Post: RE: ADC3642: DCLK_IN generation ways
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Forum Post: RE: TI-JESD204-IP: Please reply to my email.
Hi Yun, I apologize for the delay. The access to the IP was granted and you should now be able to access the folder through the secure resources page. Regards, David Chaparro
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Forum Post: RE: ADS8681: SPI CLK to SDO Delay contradicts max. SPI Frequency.
Hi Gabriel, Please review section 7.5.4.2.3 for more detail on this mode of operation. Please also refer to figures 6-7 and 6-8. In Figure 6-7, your SCLK would be buffered internally and aligned with SDO through the RVS pin.
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Forum Post: RE: ADS127L11: ADS127L11 power supplies
Hi Chris Yes, you can use a DC/DC to directly generate the +3V3 digital supply and an LDO to generate the +5V analog. If the digital supply has a high amount of noise, it could couple into the analog inputs and degrade system noise performance. A small filter at the IOVDD pin using a ferrite and capacitor will be helpful, but it the DC/DC is already a quiet supply, <50mVpp, you probably do not need any additional filtering. For the +5V analog supply, I recommend using the TPS7A4901 (36Vinput max, high PSRR and low noise). Since you are regulating from 24V down to 5V, you will want to keep the total load current to 20mA or less to avoid a high temperature. If you will have additional loads on this device, then I would recommend moving to the TPS7A4700, which comes in a bigger package and has better thermal characteristics. Regards, Keith Nicholas Precision ADC Applications
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Forum Post: RE: AFE11612-SEP: Single Event Functional Interrupt (SEFI) Characterized
Hi Alex, Going to try to get this information to you today. I'm not 100% sure of this, but my assumption is that: 1) Yes, you will need to continuously check for these events 2) I believe you will just need to rewrite the registers, wouldn't require any resets. Thanks, Erin
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Forum Post: RE: LMP92066: LMP92066, ADDRESS 0x68, DAC0_BASEM, bit4 “POL” select: 0 or 1
Hi Qiu, Yes, that is correct. If you need polarity 1, the data in address 0x68 should be 0x01A2. Thanks, Erin
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Forum Post: RE: ADS1299：Incorrect Test Signal
Hello Chengxian, Thank you for your post. Please check your channel configuration. None of the channels are currently set to measure the internal test signal: write_byte(CH1SET, 0x05); // (0110 1000)normal operation, gain=24, use srb1*, normal input write_byte(CH2SET, 0x05); // (0110 1000)normal operation, gain=24, use srb1*, normal input write_byte(CH3SET, 0x05); // (0110 1000)normal operation, gain=24, use srb1*, normal input write_byte(CH4SET, 0x05); // (0110 1000)normal operation, gain=24, use srb1*, normal input *this should say "srb2" Regards, Ryan
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Forum Post: RE: ADS8167: ADS8167 Readings goes completely wrong after some time
We have replied your questions via email. please check your s-sharif@ti.com address, also checking the spam folder. Thank you
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Forum Post: RE: ADS127L18: Availability of ADS127L18
Hi Dana, You can order preproduction devices today from ti.com ; PADS127L18IRSHR. These parts will be the same die as the final released product. Regards, Keith
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Forum Post: RE: ADS7953: Supply Voltage and GPIO pin query
Hi Parth, +VBD is the digital supply, and sets the digital I/O levels for the SPI communication pins as well as the GPIO level. +VBD = 3.3V would result in 3.3V GPIO logic. If +VA = 3.3V, and the input range selected is 2*Vref, there is no need to supply 5V, since the input is divided down to the Vref = 2.5V. The GPIO pins can be configured as General Purpose Inputs, General Purpose Outputs, or with a reserved special function. This is described in Table 11 of the datasheet. GPIO0 and GPIO1 have multiple options to serve as alarm outputs. GPIO2 has the option to serve as a device input range selector. GPIO3 can be configured as a device power-down input. Setting the General Purpose Output status over SPI is done by providing DI03-00 in any of the "Mode Control Register" modes. Please reference the description of bits DI03-00 in Table 1, Table 2, and Table 5 of the datasheet. Pull-up resistors are optional, but are a good idea for most use cases. Source and sink currents for this device are specified at 200uA. See also https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1250845/ads7953-gpio-drive-strength Regards, Joel
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Forum Post: RE: ADS8167: ADS8167 Readings goes completely wrong after some time
Hi! Thank you! I have received your email. I will look through the issues and respond shortly. Best regards, Samiha
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Forum Post: RE: ADS8699: Internal LPF characteristics
Hi Tom, OK. Could you provide me the data of the frequency response that is printed in the datasheet, e.g. as CSV ?
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Forum Post: RE: ADS8681: SPI CLK to SDO Delay contradicts max. SPI Frequency.
Hi Tom, I assume, there will be no way around the source synchronous option. Thanks for your support and have a great day!
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Forum Post: ADS125H02EVM: C22 is 1000pF or 4700pF?
Part Number: ADS125H02EVM Tool/software: The capacitor C22 for PGA output is 1000pF in the schematic and 4700pF in the parts list. Which is actually mounted on the board? If 1000pF is mounted, do you know the part number?
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Forum Post: RE: ADS7953: Supply Voltage and GPIO pin query
Hello Joel, Thank you for the feedback. For the Analog Supply voltage: As per the attached datasheet parameters, if we select the input range 2*Vref, then +VA >= 2*Vref. Based on that Still we can provide the +VA to 3.3V? Will it measure the ADC input voltage of 3.3V? Regards, Parth
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Forum Post: AFE2256EVM: Error: Oops! Header file not found
Part Number: AFE2256EVM Other Parts Discussed in Thread: AFE2256 Tool/software: Hi Experts, I have got the afe2256evm. but when I tested it (all one's pattern), it got the error: oops header data not found. I just installed one afe2256, is that right? I install your software on win10. I correctly installed the USB, firmware, I want to get the image. But I only got the error: oops header data not found. I just installed one afe2256 on the board. even if I use the all-one test pattern, it's the same. Though it notified has error, but I tested the SPI configuration is ok!, so I think it does not matter. Please advise. Regards, Josel
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Forum Post: RE: LM98725: Glitch on ADC but no glitch on OSx
Takebayashi-san, OK, let's continue the offline communication. Thanks, Nobuhiko Wasa
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Forum Post: RE: ADS1262: Noise free bits and resolution related clarification
Dear Keith, Thank you again for the awesome technical support. Now probably the last confusion. So, with our settings, of G=32, External VRef = 1.25V, Supply +/-2.5V, I can conclude, that Input FSR is +/-39.0625 mV, Noise is 27nV P-P and ENOB is 21.5 bits, So the resolution will be 26.34nV. Can you pls confirm the resolution? Also, i need to confirm that as the noise level itself is 27nV the minimum detectable/measurable input voltage should be greater than 1 LSB which is greater than 27nV. Thank you in advance
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Forum Post: RE: AFE5818: AFE5818 register configurations
Do you have EVM and gui for that ? By configuring EVM you can get basic settings of device . What exactly you are looking for ? If you have any specific queries I can help on that
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Forum Post: RE: AFE5818: AFE5818 register configurations
We don't have a EVM, as shared earlier for review, we have a FPGA and a ADC interface ,wanted to know how we can configure ADC using FPGA, Like what all registers are required to configure for ADC to start functioning, if u have any reference it would be great
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