Hi Erin, Thanks for sharing the abstract, it helps explain the SET effect and allows us to design a better implementation of the AFE11612-SEP. I am still confused about what the term "Single-event functional interrupt (SEFI) characterized up to LET = 43 MeV-cm2 /mg" specified in the first page of the AFE11612-SEP datasheet. The abstract briefly mentions increased current draw due to register flips: "The supply current excursions seen were due to register flips experienced by device which resulted in configuration change of device as shown in the Figure 3 & 4." The next sentence follows with: "The supply currents returned back to prebeam levels after reconfiguring the device to original register settings.". What I am trying to understand is twofold: 1.) Do we need continuously check and reset of the AFE11612 configuration due to SEFI/SEUs to ensure the DAC outputs do not change from their set value? 2.) If the device does experience SEFI/SEU event, what is required for recovery? A.) Rewriting/reconfiguring the devices registers? B.) Resetting the device via nRESET pin and then rewriting/reconfiguring the registers? or C.) Power cycling the device and then rewriting/reconfiguring the registers. Our application consists of feeding the DAC signal into a low bandwidth power amplifier which is used to drive mechanical actuators and precisely position optical components. The application can not afford physical changes to these optical components due to SEE effects on the DAC driving them. My takeaway from the abstract is that we should be frequently re-writing the DAC registers to the correct value in case they get flipped. We should also add a low pass filter to the DAC outputs to help mitigate fast DAC glitches from coupling into the amplifier. Does this sound reasonable or should we be looking at another device that is less susceptible to glitches on the DAC output? Thanks for your help, - Alex
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Forum Post: RE: AFE11612-SEP: Single Event Functional Interrupt (SEFI) Characterized
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Forum Post: DDC264EVM: Difference between channel A and B
Part Number: DDC264EVM Tool/software: Hi Experts, I have a question about DDC264EVM software. 1. On the software, what is the difference between channel A and B 2. Another question is about the "nDVALID Read" on the software. The default setting for this parameter is 1024. When I save the data, I see there are 512 values for each channel in A and B. Does the average codes read on the software come from the average of the 512 codes? 3.Also, why are 512 values for each channel since the setting is 1024? Does it mean that 512 values for A plus 512 values for B equals the setting in "nDVALID Read"? Do the 512 values for each channel arrange in chronological order? and each value's integration time is the same as it shows (such as 320 us)? Thank you in advance. Best regards, Jonathan
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Forum Post: RE: ADS1299: Regarding the testing of external large signals
Hi Di, This is fine. You can refer to the schematic for our ADS1299 EVM (ADS1299EEGFE-PDK) where we have shown a similar buffer option for the reference electrode. Regards, Ryan
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Forum Post: ADS131M02: Data Ready Interrupts do not occur at the right frequency
Part Number: ADS131M02 Tool/software: Hello, I am able to successfully read the ADC values. However, I'm not seeing the correct data rate frequency as mentioned in the datasheet. Here's some background on my setup. I have the CLKIN frequency set to 5.102MHz. The idea behind choosing this clock was to sync the data rates to an ISR we have that's running at 39.86KHz. The formula in the datasheet for the data rate with an OSR of 64 is: Data rate = (CLKIN / 2 * OSR) = (5.102 / 2 * 64) = 5.102 / 128 = 39.86Ksps. However, we see the DRDY interrupts occur very haphazardly. I see the first interrupt come in at 95.31KHz and the second at 68.87KHz, and this pattern repeats. The ADC is set to 16-bit mode and 64 OSR correctly. However, if I change the OSR to 128, and set the DRDY_FMT bit to 1 or 0, the interrupt occurs at my desired frequency correctly: So is the data rate actually = CLKIN / OSR? Please clarify. Am I doing something wrong here?
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Forum Post: RE: AMC1305L25: VCAP pin
Hi Brian, VCAP voltage is typically 3.45V so I don't think the TVS would help much here under normal conditions. Are they seeing noise beyond 5.48V on this pin? Filtering at LDOIN may be more effective.
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Forum Post: RE: ADS1299: Regarding the conversion of read data into actual voltage values
Hi Di, The MSB of the 24-bit binary output will tell you if the result is positive or negative. When it is positive, you simply multiply the decimal equivalent value by the LSB size (codes x V/code). When the value is negative, you must first subtract 2^24 from the decimal equivalent, and then multiply by the LSB. Again - the process is the same for both single-ended and differential input signals. To the ADC channels in ADS1299, everything is treated as "differential." Regards, Ryan
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Forum Post: RE: ADS1296R: CH4 as PACE input noisy
Hi Raghavendra, In case it is easier to share details offline, I will reach out to you via email. Understood that you are probing the PACE_OUT signals after the external amplifier on your PCB. I can see how the transients are getting close to the 200-mV detection threshold. This issue still seems unique to CH4 = PACE_OUT1 in your system. Is it possible to move the same IN4P and IN4N electrodes to another even numbered channel (i.e. CH2, CH6, or CH8)? Leave everything else in the setup the same. Regards, Ryan
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Forum Post: RE: TI-JESD204-IP: Project Error Using Vivado 2024.1
Hi Erivelton, Using the TI_204c_IP.svp file is required in order for the project to work. Using only the '_entity.sv' file will not work as this file will only have the ports used by the .svp file and should not be imported to the design. I have send an email in regards to your request for the latest IP. Once we have your response we can grant you access. With the access then you can use our latest version of the IP which has an updated encryption to work with newer versions of Vivado. Regards, David Chaparro
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Forum Post: RE: DAC8811: The output data is incorrect
the vcc is 3.3v . vp is +5v I have confirmed that the vcc and +5v voltage is stable I will be testing multiple boards these days
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Forum Post: RE: TIPD158: apply the TIPD158 evb
Hi Alex, We do not have these boards available to ship as only a few were made originally for the test of the reference design. Best, Katlynne Jones
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Forum Post: RE: ADS1299: Regarding the conversion of read data into actual voltage values
Thank you very much for your reply, I understand. Thank you again.
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Forum Post: ADS9110: The small signal output is incorrect
Part Number: ADS9110 Tool/software: I use ADS9110 to collect data, and when the data gradually increases from 0.6V, it shows that the printed data is correct. However, when the data decreases from 0.6V, the printed data remains at 0.6V (the data is constantly changing, but it is basically around 0.6V). I don't understand where this problem lies Here are the timing sequences of SCLK and SDO (I did not modify any registers, all using default settings)
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Forum Post: DAC8760: DAC 8760 interface with ESP 32
Part Number: DAC8760 Tool/software: Hello everyone, I've been trying to Interface DAC8760 to an ESP 32 for testing out the DAC in order to implement in our circuit. I used the following connections- MOSI(GPIO23) - DIN MISO(GPIO19) - SD0 SCLK(GPIO18) - SCLK CS (GPIO05) - LATCH I supplied +24v to AVDD pin and -24v to ground, both ground pins of esp and dac were connected. I tried using the following code #include #define MOSI_PIN 23 // GPIO23 for MOSI #define SCLK_PIN 18 // GPIO18 for SCLK #define CS_PIN 5 // GPIO5 for CS (Chip Select) #define MISO_PIN 19 // GPIO19 for MISO // DAC8760 register addresses #define DAC_WRITE_CR 0x02 // Control Register address #define DAC_READ_STATUS 0x05 // Status Register address // Initialize SPI and DAC void setup() { Serial.begin(9600); // Set up SPI pins SPI.begin(SCLK_PIN, MISO_PIN, MOSI_PIN, CS_PIN); // Initialize DAC8760 pinMode(CS_PIN, OUTPUT); digitalWrite(CS_PIN, HIGH); // Send initialization commands to DAC8760 dac8760Init(); } void loop() { // Read status register to check initialization status uint8_t status = readDACStatus(); Serial.print("DAC Status: "); Serial.println(status, HEX); delay(1000); // Check status every 1 second } // Function to initialize the DAC8760 void dac8760Init() { // Write to Control Register (Configure DAC for current output 4-20 mA) // Data to write: Bit 15 (DAC Enable) = 1, Bit 13-11 (Output Range) = 100 for 4-20 mA digitalWrite(CS_PIN, LOW); // Select DAC SPI.transfer(DAC_WRITE_CR); // Send command to write to Control Register SPI.transfer(0xA0); // High byte: 0xA0 (DAC Enable, 4-20mA output range) SPI.transfer(0x00); // Low byte: 0x00 (No additional configurations in low byte) digitalWrite(CS_PIN, HIGH); // Deselect DAC // Optionally, you could write again for different configurations (e.g., for voltage output) // This example configures for 4-20mA current output } // Function to read DAC status register uint8_t readDACStatus() { uint8_t status; digitalWrite(CS_PIN, LOW); // Select DAC SPI.transfer(DAC_READ_STATUS | 0x80); // Send command to read status register (with MSB = 1 for read) status = SPI.transfer(0x00); // Receive status byte digitalWrite(CS_PIN, HIGH); // Deselect DAC return status; } i was not able to receive both 4-20 mA output and voltage output. i also checked the internal reference voltage which turned out to be a stable 5v. Is there anything i am missing? Thank you in advance. Regards, Abisheik
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Forum Post: RE: ADS131M02: Data Ready Interrupts do not occur at the right frequency
Hi Dheera j , Your calculation for the output data rate is correct. The difference between these timing diagrams you shared is your /CS in the 1st timing is kept low after the next /DRDY pulse arrives. Do you read data from the ADC by checking the falling edge of the /DRDY? BR, Dale
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Forum Post: RE: ADS131A04: Non-linear Response
Hi James, For the 4th option, do you mean your signal to the ADC's input is sweeping at +1.25V DC (VCM) and the differential voltage is +/-2.2V? Is the ADC still powered with +/-2.5V power supply? BR, Dale
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Forum Post: RE: LMP92066: LMP92066, ADDRESS 0x68, DAC0_BASEM, bit4 “POL” select: 0 or 1
So when POL is set "1" and base[11:8] is A2, address 0x68 should be set 0x01A2, not 0x00A2, am I right? Thanks.
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Forum Post: RE: ADS131M02: Data Ready Interrupts do not occur at the right frequency
Hi Dheera j , I also want to add a few additional details. The DRDYn pin indication is "blocked" while you are reading conversion data. I assume you are reading the conversion data in your first diagram. That is why you see the DRDYn pin high-low transition after you read out the data from both ADC channels. Ideally you should read out conversion data before the next conversion result completes. In your first diagram you are reading data slower than the conversion period. I would also like to point you to the description of the DRDYn pin behavior which is currently only described in the AMC131M02 datasheet in the "8.5.4 ADC Output Buffer and FIFO Buffer" section. We will add this information to the ADS131M02 datasheet in the next revision as well. Regards, Joachim Wuerker
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Forum Post: RE: ADS7038: Unlock thread
That's strange; I just clicked the thread link https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1400970/ads7038-erroneous-adc-values-being-returned and it said the thread was locked. I even did a Ctrl+F5 to ensure that I wasn't using a cached version of the page. Can you please check again.
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Forum Post: ADS7960-Q1: Question about a reference voltage
Part Number: ADS7960-Q1 Tool/software: Hi Team Can this ADS7960-Q1 set the reference voltage at 300mV ? Best Regards
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Forum Post: RE: DAC8811: The output data is incorrect
I have tested multiple boards and the results are the same
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