also given Default commands(RESET, WAKEUP and Unlock) to see the Response as mentioned in Manual.

Part Number: AFE4960PEVM Tool/software: Hi, We have purchased AFE4960PEVM board. I am using the EVM board to capture ECG waveform in Biosensing application. I am able to capture the wave for ECG 1 and ECG 2, but for DUAL-AFE with 5 leads I'm getting Reset property not found error in both AFE1 and AFE2. I have attached the screenshot of the Log for your reference. Regards, Iasikha V.

Part Number: ADS131A02 Tool/software: Hello, I am using an ADS131A02 and an ESP32-PICO-KIT for my project. In this case, the ADS131A02 is in synchronous slave interface mode, as I will be using SCLK as iCLK. The problem is that I cannot get a response different from "0x7F8100" in the SPI communication. I have attached the circuit schematic: It is also important to consider everything shown in the image, as it contains all the proposed configurations. One of the most important is that the word size is 24 bits, with hamming disabled, SCLK as iCLK, no charge pump. Finally, I do not have a pull-up resistor for the CS pin because I am using the internal pull-up of pin 15 (CS0). I have also attached the code used: #include #include "esp_log.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "driver/gpio.h" #include "driver/spi_master.h" /* Define GPIO Pins for MOSI and MISO, and SCLK PIN */ #define HSPI_MOSI_GPI 13 #define HSPI_MISO_GPI 12 #define HSPI_SCLK 14 #define HSPI_CS 15 /* Define REG'S for SPI Communications */ //Read Only ID Registers #define ID_MSB_REG 0x00 //ID Control Register MSB #define ID_LSB_REG 0x01 //ID Control Register LSB //Status Registers #define STAT_1_REG 0x02 //Status 1 Register. (This register is automatically transferred on the command status response when the NULL command is sent.) #define STAT_P_REG 0x03 //Positive Input Fault Detect Status Register (exceeds the threshold set by the COMP_TH[2:0] bits) #define STAT_N_REG 0x04 //Negative Input Fault Detect Status Register (exceeds the threshold set by the COMP_TH[2:0] bits) #define STAT_S_REG 0x05 //SPI Status Register #define ERROR_CNT_REG 0x06 //Error Count Register. This register counts the Hamming and CRC errors. #define STATM2_REG 0x07 //Hardware Mode Pin Status Register //User Configuration Registers #define A_SYS_CFG_REG 0x0B //Analog System Configuration Register #define D_SYS_CFG_REG 0x0C //Digital System Configuration Register #define CLK1_REG 0x0D //Clock Configuration 1 Register #define CLK2_REG 0x0E //Clock Configuration 2 Register #define ADC_ENA_REG 0x0F //ADC Channel Enable Register #define ADC1_REG 0x11 //ADC Channel 1 Digital Gain Configuration Register #define ADC2_REG 0x12 //ADC Channel 2 Digital Gain Configuration Registers /* Define device to handle*/ spi_device_handle_t spi_device_handle ; /* Function init_spi for configure SPI*/ static esp_err_t init_spi ( void ) { /* BUS CONFIG FOR INIT */ spi_bus_config_t spi_bus_config = {}; spi_bus_config . mosi_io_num = HSPI_MOSI_GPI ; // GPIO pin for Master Out Slave In (=spi_d) signal spi_bus_config . data0_io_num = - 1 ; // GPIO pin for spi data0 signal in quad/octal mode spi_bus_config . miso_io_num = HSPI_MISO_GPI ; // GPIO pin for Master In Slave Out (=spi_q) signal spi_bus_config . data1_io_num = - 1 ; // GPIO pin for spi data1 signal in quad/octal mode spi_bus_config . sclk_io_num = HSPI_SCLK ; // GPIO pin for SPI Clock signal spi_bus_config . quadwp_io_num = - 1 ; // GPIO pin for WP (Write Protect) signal spi_bus_config . data2_io_num = - 1 ; // GPIO pin for spi data2 signal in quad/octal mode spi_bus_config . quadhd_io_num = - 1 ; // GPIO pin for HD (Hold) signal spi_bus_config . data3_io_num = - 1 ; // GPIO pin for spi data3 signal in quad/octal mode spi_bus_config . data4_io_num = - 1 ; // GPIO pin for spi data4 signal in octal mode spi_bus_config . data5_io_num = - 1 ; // GPIO pin for spi data5 signal in octal mode spi_bus_config . data6_io_num = - 1 ; // GPIO pin for spi data6 signal in octal mode spi_bus_config . data7_io_num = - 1 ; // GPIO pin for spi data7 signal in octal mode spi_bus_config . max_transfer_sz = 4092 ; // Maximum transfer size, in bytes /* DEVICE INTERFACE CONFIG FOR INIT */ spi_device_interface_config_t spi_device_interface_config = {}; spi_device_interface_config . mode = 1 ; //SPI mode, representing a pair of (CPOL, CPHA) configuration spi_device_interface_config . duty_cycle_pos = 128 ; //Duty cycle of positive clock spi_device_interface_config . clock_speed_hz = 1 * 1000 * 1000 ; //SPI clock speed in Hz spi_device_interface_config . spics_io_num = HSPI_CS ; //CS GPIO pin for this device spi_device_interface_config . queue_size = 1 ; //Transaction queue size spi_device_interface_config . pre_cb = NULL ; //Callback to be called before a transmission is started spi_device_interface_config . post_cb = NULL ; //Callback to be called after a transmission has completed spi_bus_initialize ( SPI2_HOST , & spi_bus_config , SPI_DMA_CH_AUTO ); spi_bus_add_device ( SPI2_HOST , & spi_device_interface_config , & spi_device_handle ); return ESP_OK ; } uint32_t spi_send_command ( uint16_t command_adc ) { uint32_t command = ( uint32_t ) command_adc << 8 ; // 16 bit to 24 bit uint8_t data [ 3 ] = { 0 }; // Buffer - 24 bits uint8_t zeros [ 3 ] = { 0 }; // Buffer - 24 bits // Transacción para enviar el comando spi_transaction_t spi_transaction = { . tx_buffer = & command , . rx_buffer = NULL , . length = 24 , . rxlength = 0 }; spi_device_transmit ( spi_device_handle , & spi_transaction ); spi_transaction_t spi_transaction_resp = { . tx_buffer = zeros , . rx_buffer = data , . length = 24 , . rxlength = 24 }; spi_device_transmit ( spi_device_handle , & spi_transaction_resp ); // uint32_t response = (( uint32_t ) data [ 0 ] << 16 ) | (( uint32_t ) data [ 1 ] << 8 ) | ( uint32_t ) data [ 2 ]; //uint32_t response = data; return response ; } static esp_err_t ads131a02_init ( void ) { gpio_pullup_en ( GPIO_NUM_15 ); uint32_t valor = spi_read_register ( 0x03 ); char str [ 32 ]; snprintf ( str , sizeof ( str ), " %lu " , ( unsigned long ) valor ); printf ( "Response: %s \n " , str ); return ESP_OK ; } void app_main ( void ) { ESP_ERROR_CHECK ( init_spi ()); ESP_ERROR_CHECK ( ads131a02_init ()); } I know the error could be in the programming or the schematic because when I measure the REFP value, it gives me 1.25 V by default but negative, relative to GND. The capacitors are non-polarized ceramic capacitors. I appreciate your help as I have tried to solve this and haven't been able to.

Hi Matthew, Thank you for your question. We don't have an MTBF figure in the datasheet, but we do include this plot about lifetime of the device: Please let me know if you have any more questions. Best regards, Eva

Hi Vinny, After trying this on my board, I can verify that I am experiencing the exact same issues that you are running into. I am updating the thresholds in the GUI, but it does not send anything over the I2C bus, so doesn't change the registers. If they are set in the register page, it does update the flags in the registers, but has no effect in the GUI. Unfortunately, this seems to be an issue with the software that the GUI is running on, so there won't be an immediate fix for this. I will send an update in case we're able to get an update on this. I apologize for that. Regards, Joel

Hi Iasikha - can you please share a copy of the python script as well as an image of your EVM jumper configuration? Regards, Ryan

Hi Adrien, It looks like you have access to the secure folder for the AFE4300 now. Please email biosensing_afe-support@list.ti.com if you have any additional issues. Best, Katelyn

Matt, Thanks for your valuable reply. The input frequency of 1.8 GHz is multiplied by 2 to output 3.6 GHz. After performing a reset on R0, any register reads in the GUI will be 0x00. So I'm assuming I'm doing something wrong while performing the reset. Regards, masa

Hello Joel, This is used to remote the voltage change of the NTC as the temperature changes.

Hello Geoff, Good day. Please refer to the attached file. e2e.ti.com/.../TI-DAC39-RF10-troubleshooting.zip Regards, TI-CSC

Hi Chase, I have try the output format for the SDCLKOUT3 output to LVPECL1600mV, still not work. Also I have check the lane mapping from FPGA to DAC. My understand is if the mapping is wrong, the ILAs will mismatch for LaneID between JESD IP and DAC reg config, and the link cannot be established. Is it right? Attached is my waveform now, seems noise. I will check everything again. Thanks, Daniel

That's correct we are using CPOL = 0 and CPHA = 1 configurations only. Also we are using standard SPI configuration so it the internal module which is capturing and generating the data. So I hope F280039C should generate the signal as per SPT settings CPOL = 0 and CPHA = 1 but i could not see the same. Also In the waveform above you could see the response which is wrong and not as expected. So what is the solution for this.

Hello Eric-San, Thank you very much for your quick reply. Perhaps there is a mistake in the configuration on my FPGA board. HTG830 has two FMC+ connectors, FMC+(B) seems to have a sine wave coming in, while FMC+(C) only has a sine wave coming in on one link. FMC+(B) uses one Xilinx JESD204 PHY (8 lanes) since the signals are located in the same SLR (Super Logic Region); FMC+(C) uses two PHYs (4 lanes each) since the signals span SLR0 and SLR1. Now, JESD204 parameter K is set to 32 (JMODE5=8bit single channel 8lane). So the link parameters for Xilinx JESD204 IP are set as follows. Perhaps the blocks are not well placed? K Value of ADC EVM Configuration Xilinx JESD204 IP Link Parameter Configuration Still, it is strange that in ramp mode or transport layer test mode, both links appear to be storing data correctly, but in normal mode, only one link's data is correct. If the two links were out of sync, I would expect the data to be wrong in both the transport layer test and in ramp mode, but that is not the case. ーーーーーーーーーーーーーーーーー Below are the answers to your questions. Q1. But what you are seeing is strange are you making any other modifications to the ADC at all? A1. The only change I made to the ADC EVM was to modify it according to the EVM user guide to make it an Onboard Clocking Option. www.ti.com/.../slau640 (7.2.2) Q2. From the ADC both links will be aligned, do you have any way of monitoring the link status on the FPGA side? A2. I add an ILA and monitor the output signal of the JESD204 IP to verify. (rx_frame_error etc) I am concerned about what should happen to the rx_start_of_frame, etc. for each IP when using two JESD204 PHY IPs and two JESD204 IPs, respectively, as in this case. Q3. Finally, can you let me know what FPGA FW you are using to capture data is it TI JESD 204c IP, Xilinx or some other custom solution? A3. They are listed below. ・Vivado 2020.1 ・Xilinx JESD204 PHY IP (v4.0) ・Xilinx JESD204 IP(7.2) ・FPGA Kintex Ultrascale KCU115 ・FPGA Board => HTG830 (Hitech Global) www.hitechglobal.com/.../Virtex-UltraScale-FPGA.htm ※I am not using the TI 204C IP as I am programming with an IP integrator (block design).It would be nice if an IP integrator (block design) compliant version was released. Best regards, Takeo

Thanks for confirming the behavior. I look forward to any info when you have it! In the meantime, I'll try an Aardvark device to talk to the IC and see if I can get it to work for us. Do you happen to have any python scripts for this device anywhere I can leverage? Even simple register read and conversion to voltage will help me from creating it all from scratch. Thanks Vinny

Hi, What is the end application for this ultrasound imaging system ? Based on that we can suggest appropriate solution.

Hi Ryan, Thanks for the reply. I have connected the board as suggested in the EVM User Guide and used the python script given in the AFE4960PEVM. I have attached the EVM jumper configuration image and the script for your reference. """Hard reset AFE4960 on both EVM""" reset_AFE_GUI() """AFE1 Lead construction""" AFE1.component.segment.AFE4960.AFE4960_global.SW_ECG_INP_ECG = 2 AFE1.component.segment.AFE4960.AFE4960_global.SW_ECG_INM_ECG = 8 AFE1.component.segment.AFE4960.AFE4960_global.SW_BIOZ_RXP = 5 AFE1.component.segment.AFE4960.AFE4960_global.SW_BIOZ_RXM = 6 AFE1.component.segment.AFE4960.AFE4960_global.SW_BIOZ_TXP = 1 AFE1.component.segment.AFE4960.AFE4960_global.SW_BIOZ_TXM = 2 AFE1.component.segment.AFE4960.AFE4960_global.SW_RLD = 1 """AFE2 Lead construction""" AFE2.component.segment.AFE4960.AFE4960_global.SW_ECG_INP_ECG = 2 AFE2.component.segment.AFE4960.AFE4960_global.SW_ECG_INM_ECG = 8 AFE2.component.segment.AFE4960.AFE4960_global.SW_BIOZ_RXP = 5 AFE2.component.segment.AFE4960.AFE4960_global.SW_BIOZ_RXM = 6 AFE2.component.segment.AFE4960.AFE4960_global.SW_BIOZ_TXP = 0 AFE2.component.segment.AFE4960.AFE4960_global.SW_BIOZ_TXM = 0 AFE2.component.segment.AFE4960.AFE4960_global.SW_RLD = 0 """AFE1 Signal Acquisition configuration""" AFE1.component.segment.AFE4960.AFE4960_global.COUNT_RAC = 96 AFE1.component.segment.AFE4960.AFE4960_global.REG_NUM_TS = 1 AFE1.component.segment.AFE4960.AFE4960_global.REG_NUM_ESAW = 0 AFE1.component.segment.AFE4960.AFE4960_global.REG_NUM_BSAW = 0 AFE1.component.segment.AFE4960.AFE4960_global.CONFIG_TS0 = 1 AFE1.component.segment.AFE4960.AFE4960_global.CONFIG_TS1 = 3 """AFE2 Signal Acquisition configuration""" AFE2.component.segment.AFE4960.AFE4960_global.COUNT_RAC = 96 AFE2.component.segment.AFE4960.AFE4960_global.REG_NUM_TS = 1 AFE2.component.segment.AFE4960.AFE4960_global.REG_NUM_ESAW = 0 AFE2.component.segment.AFE4960.AFE4960_global.REG_NUM_BSAW = 0 AFE2.component.segment.AFE4960.AFE4960_global.CONFIG_TS0 = 1 AFE2.component.segment.AFE4960.AFE4960_global.CONFIG_TS1 = 3 """AFE1 Signal chain configuration""" AFE1.component.segment.AFE4960.AFE4960_global.ECG_INA_GAIN = 1 AFE1.component.segment.AFE4960.AFE4960_global.EN_DEC_ECG = 1 AFE1.component.segment.AFE4960.AFE4960_global.ECG_DEC_FACTOR = 0 AFE1.component.segment.AFE4960.AFE4960_global.BIOZ_PHI_STEP = 174763 AFE1.component.segment.AFE4960.AFE4960_global.BIOZ_EXC_SQUARE = 1 AFE1.component.segment.AFE4960.AFE4960_global.BIOZ_RE = 8 AFE1.component.segment.AFE4960.AFE4960_global.BIOZ_CE = 0 AFE1.component.segment.AFE4960.AFE4960_global.SHORT_RINT_BIOZ = 1 AFE1.component.segment.AFE4960.AFE4960_global.ATTN_BIOZ_TX = 0 AFE1.component.segment.AFE4960.AFE4960_global.EN_ECG2 = 0 AFE1.component.segment.AFE4960.AFE4960_global.SEL_IN_BIOZ_RX = 0 AFE1.component.segment.AFE4960.AFE4960_global.RECONFIGURE_BIOZ_LPF = 0 AFE1.component.segment.AFE4960.AFE4960_global.EN_RLD_LOOP_ECG2 = 0 AFE1.component.segment.AFE4960.AFE4960_global.BIOZ_LPF_BW = 2 AFE1.component.segment.AFE4960.AFE4960_global.SEL_CHPF1_BIOZ = 0 AFE1.component.segment.AFE4960.AFE4960_global.SEL_RHPF1_BIOZ = 2 AFE1.component.segment.AFE4960.AFE4960_global.BIOZ_INA_GAIN = 3 AFE1.component.segment.AFE4960.AFE4960_global.PROCESS_BSAW = 0 AFE1.component.segment.AFE4960.AFE4960_global.EN_DEC_BIOZ = 1 AFE1.component.segment.AFE4960.AFE4960_global.BIOZ_DEC_FACTOR = 4 AFE1.component.segment.AFE4960.AFE4960_global.ACQ_MODE_SEL = 74 AFE1.component.segment.AFE4960.AFE4960_global.EN_ECG_RX = 1 AFE1.component.segment.AFE4960.AFE4960_global.PDN_ECG_INA = 0 AFE1.component.segment.AFE4960.AFE4960_global.PDN_ECG_RLD = 0 AFE1.component.segment.AFE4960.AFE4960_global.PDN_ADC = 0 AFE1.component.segment.AFE4960.AFE4960_global.PDN_OSCH = 0 AFE1.component.segment.AFE4960.AFE4960_global.PDN_ILEAD = 0 AFE1.component.segment.AFE4960.AFE4960_global.EN_BIOZ_RX = 1 AFE1.component.segment.AFE4960.AFE4960_global.EN_BIOZ_TX = 1 AFE1.component.segment.AFE4960.AFE4960_global.DIS_ACTIVE_BIOZ_TX = 0 AFE1.component.segment.AFE4960.AFE4960_global.DIS_BUF_PDN_ON_ADC = 1 AFE1.component.segment.AFE4960.AFE4960_global.DIS_PD_REFSYS = 1 AFE1.component.segment.AFE4960.AFE4960_global.DIS_PD_VCM = 1 AFE1.component.segment.AFE4960.AFE4960_global.PDNAFE = 0 AFE1.component.segment.AFE4960.AFE4960_global.PDN_BG_IN_DEEP_SLEEP = 0 AFE1.component.segment.AFE4960.AFE4960_global.DIS_CHOP_INA1 = 0 AFE1.component.segment.AFE4960.AFE4960_global.DIS_CHOP_INA2 = 0 AFE1.component.segment.AFE4960.AFE4960_global.TIMER_ENABLE = 1 AFE1.component.segment.AFE4960.AFE4960_global.RAC_COUNTER_ENABLE = 1 AFE1.component.segment.AFE4960.AFE4960_global.FIFO_EN = 1 AFE1.component.segment.AFE4960.AFE4960_global.REG_WM_FIFO = 0 """AFE2 Signal chain configuration""" AFE2.component.segment.AFE4960.AFE4960_global.ECG_INA_GAIN = 1 AFE2.component.segment.AFE4960.AFE4960_global.EN_DEC_ECG = 1 AFE2.component.segment.AFE4960.AFE4960_global.ECG_DEC_FACTOR = 0 AFE2.component.segment.AFE4960.AFE4960_global.EN_ECG2 = 1 AFE2.component.segment.AFE4960.AFE4960_global.SEL_IN_BIOZ_RX = 1 AFE2.component.segment.AFE4960.AFE4960_global.RECONFIGURE_BIOZ_LPF = 1 AFE2.component.segment.AFE4960.AFE4960_global.EN_RLD_LOOP_ECG2 = 0 AFE2.component.segment.AFE4960.AFE4960_global.BIOZ_LPF_BW = 2 AFE2.component.segment.AFE4960.AFE4960_global.SEL_CHPF1_BIOZ = 0 AFE2.component.segment.AFE4960.AFE4960_global.SEL_RHPF1_BIOZ = 2 AFE2.component.segment.AFE4960.AFE4960_global.BIOZ_INA_GAIN = 0 AFE2.component.segment.AFE4960.AFE4960_global.PROCESS_BSAW = 3 AFE2.component.segment.AFE4960.AFE4960_global.EN_DEC_BIOZ = 1 AFE2.component.segment.AFE4960.AFE4960_global.BIOZ_DEC_FACTOR = 0 AFE2.component.segment.AFE4960.AFE4960_global.ACQ_MODE_SEL = 74 AFE2.component.segment.AFE4960.AFE4960_global.EN_ECG_RX = 1 AFE2.component.segment.AFE4960.AFE4960_global.PDN_ECG_INA = 0 AFE2.component.segment.AFE4960.AFE4960_global.PDN_ECG_RLD = 0 AFE2.component.segment.AFE4960.AFE4960_global.PDN_ADC = 0 AFE2.component.segment.AFE4960.AFE4960_global.PDN_OSCH = 0 AFE2.component.segment.AFE4960.AFE4960_global.PDN_ILEAD = 0 AFE2.component.segment.AFE4960.AFE4960_global.EN_BIOZ_RX = 1 AFE2.component.segment.AFE4960.AFE4960_global.EN_BIOZ_TX = 1 AFE2.component.segment.AFE4960.AFE4960_global.DIS_ACTIVE_BIOZ_TX = 1 AFE2.component.segment.AFE4960.AFE4960_global.DIS_BUF_PDN_ON_ADC = 1 AFE2.component.segment.AFE4960.AFE4960_global.DIS_PD_REFSYS = 1 AFE2.component.segment.AFE4960.AFE4960_global.DIS_PD_VCM = 1 AFE2.component.segment.AFE4960.AFE4960_global.PDNAFE = 0 AFE2.component.segment.AFE4960.AFE4960_global.PDN_BG_IN_DEEP_SLEEP = 0 AFE2.component.segment.AFE4960.AFE4960_global.DIS_CHOP_INA1 = 0 AFE2.component.segment.AFE4960.AFE4960_global.DIS_CHOP_INA2 = 0 AFE2.component.segment.AFE4960.AFE4960_global.TIMER_ENABLE = 1 AFE2.component.segment.AFE4960.AFE4960_global.RAC_COUNTER_ENABLE = 1 AFE2.component.segment.AFE4960.AFE4960_global.FIFO_EN = 1 AFE2.component.segment.AFE4960.AFE4960_global.REG_WM_FIFO = 0 """AFE1 Pace pulse detect configuration""" AFE1.component.segment.AFE4960.AFE4960_global.EN_PACE = 1 AFE1.component.segment.AFE4960.AFE4960_global.PACE_SET_HIGH_2 = 1 AFE1.component.segment.AFE4960.AFE4960_global.PACE_SET_HIGH_1 = 1 AFE1.component.segment.AFE4960.AFE4960_global.PACE_SET_HIGH_0 = 1 AFE1.component.segment.AFE4960.AFE4960_global.PACE_CONFIG_REG1 = 995684 AFE1.component.segment.AFE4960.AFE4960_global.PACE_CONFIG_REG2 = 1048256 AFE1.component.segment.AFE4960.AFE4960_global.PACE_DIS_RESP_REJECT = 0 AFE1.component.segment.AFE4960.AFE4960_global.SEL_CLK_PACE = 0 AFE1.component.segment.AFE4960.AFE4960_global.WIDTH_PACE_MIN = 4 AFE1.component.segment.AFE4960.AFE4960_global.WIDTH_PACE_MAX = 135 AFE1.component.segment.AFE4960.AFE4960_global.PACE_OBS_EXTEND = 1 AFE1.component.segment.AFE4960.AFE4960_global.PACE_VALID_COMPLETE = 1 AFE1.component.segment.AFE4960.AFE4960_global.PACE_REF1_H = 2 AFE1.component.segment.AFE4960.AFE4960_global.PACE_REF1_L = 2 AFE1.component.segment.AFE4960.AFE4960_global.PACE_FIFO_DATA_CTRL = 0 AFE1.component.segment.AFE4960.AFE4960_global.EN_PACE_WINDOW_ADC_RDY = 0 AFE1.component.segment.AFE4960.AFE4960_global.EN_PACE_WINDOW_GPIO2 = 0 AFE1.component.segment.AFE4960.AFE4960_global.EN_PACE_VALID_TAG = 1 AFE1.component.segment.AFE4960.AFE4960_global.EN_PACE_OVERLAP_TAG = 0 AFE1.component.segment.AFE4960.AFE4960_global.USE_PACE_OVERLAP_TAG = 0 AFE1.component.segment.AFE4960.AFE4960_global.USE_BOTH_PACE_TAGS = 0 AFE1.component.segment.AFE4960.AFE4960_global.EN_PACE_TAG_ECG_CH1 = 1 AFE1.component.segment.AFE4960.AFE4960_global.EN_PACE_TAG_ECG_CH2 = 1 """AFE2 Pace pulse detect configuration""" AFE2.component.segment.AFE4960.AFE4960_global.EN_PACE = 1 AFE2.component.segment.AFE4960.AFE4960_global.PACE_SET_HIGH_2 = 1 AFE2.component.segment.AFE4960.AFE4960_global.PACE_SET_HIGH_1 = 1 AFE2.component.segment.AFE4960.AFE4960_global.PACE_SET_HIGH_0 = 1 AFE2.component.segment.AFE4960.AFE4960_global.PACE_CONFIG_REG1 = 995684 AFE2.component.segment.AFE4960.AFE4960_global.PACE_CONFIG_REG2 = 1048256 AFE2.component.segment.AFE4960.AFE4960_global.PACE_DIS_RESP_REJECT = 1 AFE2.component.segment.AFE4960.AFE4960_global.SEL_CLK_PACE = 0 AFE2.component.segment.AFE4960.AFE4960_global.WIDTH_PACE_MIN = 4 AFE2.component.segment.AFE4960.AFE4960_global.WIDTH_PACE_MAX = 135 AFE2.component.segment.AFE4960.AFE4960_global.PACE_OBS_EXTEND = 1 AFE2.component.segment.AFE4960.AFE4960_global.PACE_VALID_COMPLETE = 1 AFE2.component.segment.AFE4960.AFE4960_global.PACE_REF1_H = 2 AFE2.component.segment.AFE4960.AFE4960_global.PACE_REF1_L = 2 AFE2.component.segment.AFE4960.AFE4960_global.PACE_FIFO_DATA_CTRL = 0 AFE2.component.segment.AFE4960.AFE4960_global.EN_PACE_WINDOW_ADC_RDY = 0 AFE2.component.segment.AFE4960.AFE4960_global.EN_PACE_WINDOW_GPIO2 = 0 AFE2.component.segment.AFE4960.AFE4960_global.EN_PACE_VALID_TAG = 1 AFE2.component.segment.AFE4960.AFE4960_global.EN_PACE_OVERLAP_TAG = 0 AFE2.component.segment.AFE4960.AFE4960_global.USE_PACE_OVERLAP_TAG = 0 AFE2.component.segment.AFE4960.AFE4960_global.USE_BOTH_PACE_TAGS = 0 AFE2.component.segment.AFE4960.AFE4960_global.EN_PACE_TAG_ECG_CH1 = 1 AFE2.component.segment.AFE4960.AFE4960_global.EN_PACE_TAG_ECG_CH2 = 1 """AFE1 Interrupt configuration""" AFE1.component.segment.AFE4960.AFE4960_global.MASK_DC_LEAD_DET = 0 AFE1.component.segment.AFE4960.AFE4960_global.MASK_AC_LEAD_ON = 1 AFE1.component.segment.AFE4960.AFE4960_global.MASK_AC_LEAD_OFF = 1 AFE1.component.segment.AFE4960.AFE4960_global.MASK_ADC_FIFO_RDY = 1 AFE1.component.segment.AFE4960.AFE4960_global.MASK_PACE_VALID_INT = 0 AFE1.component.segment.AFE4960.AFE4960_global.MASK_DISABLE1 = 1 AFE1.component.segment.AFE4960.AFE4960_global.MASK_DISABLE2 = 1 """AFE2 Interrupt configuration""" AFE2.component.segment.AFE4960.AFE4960_global.INT_MUX_ADC_RDY_1 = 2 AFE2.component.segment.AFE4960.AFE4960_global.MASK_DC_LEAD_DET = 0 AFE2.component.segment.AFE4960.AFE4960_global.MASK_AC_LEAD_ON = 1 AFE2.component.segment.AFE4960.AFE4960_global.MASK_AC_LEAD_OFF = 1 AFE2.component.segment.AFE4960.AFE4960_global.MASK_ADC_FIFO_RDY = 1 AFE2.component.segment.AFE4960.AFE4960_global.MASK_PACE_VALID_INT = 0 AFE2.component.segment.AFE4960.AFE4960_global.MASK_DISABLE1 = 1 AFE2.component.segment.AFE4960.AFE4960_global.MASK_DISABLE2 = 1 """AFE1 128K CLK ON GPIO2""" AFE1.component.segment.AFE4960.AFE4960_global.EN_GPIO2_OUT = 1 AFE1.component.segment.AFE4960.AFE4960_global.INT_MUX_GPIO2_2 = 0 AFE1.component.segment.AFE4960.AFE4960_global.INT_MUX_GPIO2_1 = 0 AFE1.component.segment.AFE4960.AFE4960_global.EN_128K_CLKOUT = 1 """AFE1 RAC RST OUT ON ADC RDY""" AFE1.component.segment.AFE4960.AFE4960_global.INT_MUX_ADC_RDY_2 = 1 AFE1.component.segment.AFE4960.AFE4960_global.INT_MUX_ADC_RDY_1 = 3 AFE1.component.segment.AFE4960.AFE4960_global.INPUT_OUTPUT_RAC_RST = 1 """AFE2 RAC RST IN ON GPIO2""" AFE2.component.segment.AFE4960.AFE4960_global.EN_GPIO2_IN = 1 AFE2.component.segment.AFE4960.AFE4960_global.EN_GPIO2_OUT = 0 AFE2.component.segment.AFE4960.AFE4960_global.INT_MUX_GPIO2_2 = 0 AFE2.component.segment.AFE4960.AFE4960_global.INT_MUX_GPIO2_1 = 0 AFE2.component.segment.AFE4960.AFE4960_global.INPUT_OUTPUT_RAC_RST = 3 """AFE1 Clocking configuration""" AFE1.component.segment.AFE4960.AFE4960_global.SEL2_CLK_TE = 1 AFE1.component.segment.AFE4960.AFE4960_global.OSCL_DIS = 1 AFE1.component.segment.AFE4960.AFE4960_global.EN_OSCL_SYNC = 0 AFE1.component.segment.AFE4960.AFE4960_global.DIS_DYN_PDN_OSCH = 1 AFE1.component.segment.AFE4960.AFE4960_global.SEL1_CLK_BIOZ = 1 AFE1.component.segment.AFE4960.AFE4960_global.SEL2_CLK_BIOZ = 1 AFE1.component.segment.AFE4960.AFE4960_global.EN_PLL = 1 AFE1.component.segment.AFE4960.AFE4960_global.SEL2_CLK_RAC = 1 AFE1.component.segment.AFE4960.AFE4960_global.SEL1_CLK_RAC = 0 AFE1.component.segment.AFE4960.AFE4960_global.SEL1_CLK_TE = 0 AFE1.component.segment.AFE4960.AFE4960_global.DIV_TE_RAC_OUT_EN = 1 AFE1.component.segment.AFE4960.AFE4960_global.DIV_IN_BIOZ = 0 AFE1.component.segment.AFE4960.AFE4960_global.DIV_FB_PLL = 4 AFE1.component.segment.AFE4960.AFE4960_global.DIV_OUT_RAC = 1 AFE1.component.segment.AFE4960.AFE4960_global.DIV_OUT_BIOZ = 2 """AFE2 Clocking configuration""" AFE2.component.segment.AFE4960.AFE4960_global.SEL2_CLK_TE = 0 AFE2.component.segment.AFE4960.AFE4960_global.OSCL_DIS = 1 AFE2.component.segment.AFE4960.AFE4960_global.EN_OSCL_SYNC = 0 AFE2.component.segment.AFE4960.AFE4960_global.DIS_DYN_PDN_OSCH = 0 AFE2.component.segment.AFE4960.AFE4960_global.SEL1_CLK_BIOZ = 1 AFE2.component.segment.AFE4960.AFE4960_global.SEL2_CLK_BIOZ = 0 AFE2.component.segment.AFE4960.AFE4960_global.EN_PLL = 0 AFE2.component.segment.AFE4960.AFE4960_global.SEL2_CLK_RAC = 0 AFE2.component.segment.AFE4960.AFE4960_global.SEL1_CLK_RAC = 1 AFE2.component.segment.AFE4960.AFE4960_global.SEL1_CLK_TE = 1 AFE2.component.segment.AFE4960.AFE4960_global.DIV_TE_RAC_OUT_EN = 0 AFE2.component.segment.AFE4960.AFE4960_global.DIV_IN_BIOZ = 0 AFE2.component.segment.AFE4960.AFE4960_global.DIV_FB_PLL = 0 AFE2.component.segment.AFE4960.AFE4960_global.DIV_OUT_RAC = 0 AFE2.component.segment.AFE4960.AFE4960_global.DIV_OUT_BIOZ = 0 """AFE1 DC Lead Detection Configuration """ AFE1.component.segment.AFE4960.AFE4960_global.SW_RBIAS1_ECGP = 1 AFE1.component.segment.AFE4960.AFE4960_global.SW_RBIAS1_LEAD_BIAS = 1 AFE1.component.segment.AFE4960.AFE4960_global.POL_RBIAS1_LEAD_BIAS = 0 AFE1.component.segment.AFE4960.AFE4960_global.SW_RBIAS2_ECGM = 1 AFE1.component.segment.AFE4960.AFE4960_global.SW_RBIAS2_LEAD_BIAS = 1 AFE1.component.segment.AFE4960.AFE4960_global.POL_RBIAS2_LEAD_BIAS = 1 AFE1.component.segment.AFE4960.AFE4960_global.SW_RBIAS3_ECG1 = 3 AFE1.component.segment.AFE4960.AFE4960_global.SW_RBIAS3_LEAD_BIAS = 1 AFE1.component.segment.AFE4960.AFE4960_global.POL_RBIAS3_LEAD_BIAS = 0 AFE1.component.segment.AFE4960.AFE4960_global.SW_RBIAS4_ECG2 = 3 AFE1.component.segment.AFE4960.AFE4960_global.SW_RBIAS4_LEAD_BIAS = 0 AFE1.component.segment.AFE4960.AFE4960_global.POL_RBIAS4_LEAD_BIAS = 0 AFE1.component.segment.AFE4960.AFE4960_global.SEL_RBIAS_CH1 = 0 AFE1.component.segment.AFE4960.AFE4960_global.SEL_RBIAS_CH2 = 0 AFE1.component.segment.AFE4960.AFE4960_global.LEAD_DET_THR_L = 3 AFE1.component.segment.AFE4960.AFE4960_global.LEAD_DET_THR_H = 3 AFE1.component.segment.AFE4960.AFE4960_global.EN_COMP_ANA = 1 AFE1.component.segment.AFE4960.AFE4960_global.LEAD_DET_MODULE_CLK_EN = 1 AFE1.component.segment.AFE4960.AFE4960_global.LEAD_DET_WIDTH = 100 """AFE2 DC Lead Detection Configuration """ AFE2.component.segment.AFE4960.AFE4960_global.SW_RBIAS1_ECGP = 1 AFE2.component.segment.AFE4960.AFE4960_global.SW_RBIAS1_LEAD_BIAS = 1 AFE2.component.segment.AFE4960.AFE4960_global.POL_RBIAS1_LEAD_BIAS = 0 AFE2.component.segment.AFE4960.AFE4960_global.SW_RBIAS2_ECGM = 1 AFE2.component.segment.AFE4960.AFE4960_global.SW_RBIAS2_LEAD_BIAS = 1 AFE2.component.segment.AFE4960.AFE4960_global.POL_RBIAS2_LEAD_BIAS = 1 AFE2.component.segment.AFE4960.AFE4960_global.SW_RBIAS3_ECG1 = 3 AFE2.component.segment.AFE4960.AFE4960_global.SW_RBIAS3_LEAD_BIAS = 1 AFE2.component.segment.AFE4960.AFE4960_global.POL_RBIAS3_LEAD_BIAS = 0 AFE2.component.segment.AFE4960.AFE4960_global.SW_RBIAS4_ECG2 = 3 AFE2.component.segment.AFE4960.AFE4960_global.SW_RBIAS4_LEAD_BIAS = 0 AFE2.component.segment.AFE4960.AFE4960_global.POL_RBIAS4_LEAD_BIAS = 0 AFE2.component.segment.AFE4960.AFE4960_global.SEL_RBIAS_CH1 = 0 AFE2.component.segment.AFE4960.AFE4960_global.SEL_RBIAS_CH2 = 0 AFE2.component.segment.AFE4960.AFE4960_global.LEAD_DET_THR_L = 3 AFE2.component.segment.AFE4960.AFE4960_global.LEAD_DET_THR_H = 3 AFE2.component.segment.AFE4960.AFE4960_global.EN_COMP_ANA = 1 AFE2.component.segment.AFE4960.AFE4960_global.LEAD_DET_MODULE_CLK_EN = 1 AFE2.component.segment.AFE4960.AFE4960_global.LEAD_DET_WIDTH = 100 """Software requirements""" """Update the sequence of data in FIFO""" FIFO_ORDER_AFE1 = np.array(["AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_ECG_CH1", \ "AFE1_RESP_I", "AFE1_RESP_Q"]) FIFO_ORDER_AFE2 = np.array(["AFE2_ECG_CH1","AFE2_ECG_CH2"]) FIFO_ORDER_AFE1 = np.array(["AFE1_ECG_CH1","AFE1_RESP_I", "AFE1_RESP_Q"]) FIFO_ORDER_AFE2 = np.array(["AFE2_ECG_CH1","AFE2_ECG_CH2"]) regCapture._controller.updateFiFoOrder(FIFO_ORDER_AFE1,FIFO_ORDER_AFE2) """Update the data rate""" dataToAddDict = {"KEY":"AFE1_ECG_CH1", "DATA_RATE":"682.666666667"} addData(dataToAddDict) dataToAddDict = {"KEY":"AFE1_ECG_CH1_RAW", "DATA_RATE":"682.666666667"} addData(dataToAddDict) dataToAddDict = {"KEY":"AFE1_RESP_I", "DATA_RATE":"42.6666666667"} addData(dataToAddDict) dataToAddDict = {"KEY":"AFE1_RESP_I_RAW", "DATA_RATE":"42.6666666667"} addData(dataToAddDict) dataToAddDict = {"KEY":"AFE1_RESP_Q", "DATA_RATE":"42.6666666667"} addData(dataToAddDict) dataToAddDict = {"KEY":"AFE1_RESP_Q_RAW", "DATA_RATE":"42.6666666667"} addData(dataToAddDict) dataToAddDict = {"KEY":"AFE2_ECG_CH1", "DATA_RATE":"682.666666667"} addData(dataToAddDict) dataToAddDict = {"KEY":"AFE2_ECG_CH1_RAW", "DATA_RATE":"682.666666667"} addData(dataToAddDict) dataToAddDict = {"KEY":"AFE2_ECG_CH2", "DATA_RATE":"682.666666667"} addData(dataToAddDict) dataToAddDict = {"KEY":"AFE2_ECG_CH2_RAW", "DATA_RATE":"682.666666667"} addData(dataToAddDict) """Mandatory register to read""" dataToAddDict = {"KEY":"REG_6D", "DATA_RATE":"682.666666667"} addData(dataToAddDict) """Additional register to read""" dataToAddDict = {"KEY":"REG_BC", "DATA_RATE":"682.666666667"} addData(dataToAddDict) """Add data for plotting""" addDataToPlot("'AFE1_ECG_CH1'", 1, filter="Disable", color=color['Blue']) addDataToPlot("AMPLITUDE('AFE1_RESP_I','AFE1_RESP_Q')", 2, filter="Disable", color=color['Maroon']) addDataToPlot("'AFE2_ECG_CH1'", 3, filter="Disable", color=color['Green']) addDataToPlot("'AFE2_ECG_CH2'", 4, filter="Disable", color=color['Maroon']) # addDataToPlot("PACE_STATUS('AFE1_REG_BC')", 3, filter="Disable", color=color['Red']) # addDataToPlot("PACE_STATUS('AFE2_REG_BC')", 4, filter="Disable", color=color['Green']) MODE = "DUAL_AFE_3ECG_1RESP" START_LEAD_STATUS_CHECK() Regards, Iasikha V.

hello , could you help give your fast confirmation quickly ? urgent case , thanks a lot

Part Number: AMC130M02 Tool/software: Hi All, I would like to know how to convert single end to differential signal. Is it possible to exchange information properly if I use AD2 fixed to GND? Or is there another good way? Input voltage of AD1 and AD2 will be in the range of 0V to 1.0V. Is it better to use differential amplifier or inversion buffer? If there is a best way, please let me know. Best Regards, Ryusuke

Hello Kadeem, Thanks for these simulation results. It confirms that the LMK03318 is a good candidate, about phase noise, for this kind of application. Next step will be to check all the other features (mainly interfaces compatibility). Regards, Alain

Hello Sachin, Thank you for your reply. We have developed a wearable, small ultrasonic transducer array and would like to use TI’s EVM to verify its imaging capabilities. Currently, the number of channels does not exceed 16. We hope to achieve transmission beamforming for the array as well as the acquisition of the corresponding echo signals for each channel. Thank you!