Hi Bryan, Yes, the ADC is affected by electromagnetic interference from the discharge. After the discharge, the ADC starts to warm up, and its 3.3V digital section supply goes to ~2V, causing both to get hotter. Regarding the same reference, I just wanted to clarify that the discharge's GND and the ADC's GND are the same. Both systems are powered by the same battery. Unfortunately, due to industrial confidentiality, I cannot provide the schematic unless we go offline.
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Forum Post: RE: ADS1256: Electromagnetic interference
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Forum Post: RE: ADS52J90: Analog input termination and coupling
Hi, The first 50 ohm and 6.8pf is not for termination . This is used to absorb sampling glitch from the device . The corner frequency of this is designed for that . This is explained in the datasheet also. Are you using ac coupling or dc coupling ?
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Forum Post: ADS1298RECGFE-PDK: Respiration Mode not working on ADS1298RECG-PDK
Part Number: ADS1298RECGFE-PDK Tool/software: currently I am working on respiration mode. where i found related documentation on ads1298revm & followed the same hardware and software configuration which is available in screenshot. but not getting desired output for respiration signal. I have also tried TI GUI version but still not getting desired output. where i have observed that there is no significant difference in waveform whether demodulation enable / disable (screenshot attached). also, I haven't found bit called pulse mode disable in CONFIG4 register and another is VREF TO VREFP in RESP Register. so, can you please guide me for this so i can proceed further? and also please guide me for how to get respiration signal?
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Forum Post: ADS1231: Behavior of ADC when reference voltage is absent
Part Number: ADS1231 Tool/software: Hi, We are using ADS1231 to interface for six wire configuration loadcell. Where excitation voltage and reference voltage is same (5V). We have below query related to ADC behavior: When six wire sensor is not connected to ADC then VREFP and VREFN pin will be floating. This means ideally no reference voltage is available on these pin, also not on AINP and AINN pin. In this case what will be the ADC output? We observed garbage values when we disconnect the loadcell sensor. Is there any fix output value will be generate by ADC? Regards, Nikhil
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Forum Post: RE: ADS112C04: external reference voltage [(VREFP – VREFN) / 4] selected as inputs to the ADC doesn't work
Hello Henry, That change on the configuration Register 1 worked. Thanks!
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Forum Post: ADS131M08: ADS131m08 SPI communication problems
Part Number: ADS131M08 Tool/software: Hello experts, i am trying to set up communication through SPI between an ads131m08 and an f280049 uC. I have big problems to understand how it should works properly. Actually i have a routine that should simply read data from the ADC. The SPI clock is set to 10MHz, the ADC clock is 8.192MHz. My steps are: 1. reset the ADC, and wait for it to exit reset. 2. starting to send NULL frames, to read datas. The frame i send is 10 words of zeroes, each word is 24 bit, since after reset adc has 24bit size word by default. My reading routine do the following: - waits for the adc signal DRDYn to go low. - i puts 15 16bit words of zeroes in the SPITXBUF of my SpiA - i wait to receive 15 words in the FIFO RX, of the SpiA. - I wait for the DRDYn signal from ADC to go up again and then repeat. What i don't understand is that the DRDYn signal seems to have unpredictable behaviour, sometimes it goes up properly after reading a frame. Sometimes it stays DOWN, and makes a very narrow pike just very before the next conversion occurs (it means the DRDYn stays low for about 244us.). Sometimes the DRDY stay low for 4ms, to the end of ADC spi timeout. What i am missing, to correctly read data from adc?? Do you have some example code, that interfaces a SPI peripheral of a uC, to this ADC?? just to make a comparison of what i am doing wrong?? Kind Regards Emanuele Peruzzi
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Forum Post: RE: DAC61402EVM: DAC61402EVM
Hi Sanjay, Thanks for the commands. We are trying to read back the register values using commands on SDO line, first we sent 0x030A84 on SDI line. then we sent 0x830000 on SDI line so that we could read back the values of 03 register, but we are not getting expected values. please find below images for same. -> Writing 0xA84 to 03 -> Writing 0x830000 (for reading register 3) -> Captured SDO, SYNC and SCLK on logic analyzer
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Forum Post: ADS7049-Q1: 4-wire SPI
Part Number: ADS7049-Q1 Tool/software: Customer is looking for the below SPEC ADC: 12BIT ADC、1MSPS、4-wire SPI, Cost effective. ADS7049 could meet the spec but it's 3-wire SPI that is not meeting customer's SPI interface. Please help to recommend a similar one with 4-wire SPI interface. thanks. Regards Brian
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Forum Post: RE: TLA2528: TLA2528
Finally I found the issue. In the I2C read function I had to set the flag which set the NAK only for the last byte read. If I set ACK or NACK for each byte the read function does not work. I have not fully understood this (it does not seems to conform to datasheet directives) but it works.
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Forum Post: RE: TLA2528: TLA2528
Finally I found the issue. In the I2C read function I had to set the flag which set the NAK only for the last byte read. If I set ACK or NACK for each byte the read function does not work. I have not fully understood this (it does not seems to conform to datasheet directives) but it works.
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Forum Post: RE: DAC61402EVM: DAC61402EVM
Hi Kiran, Your SPI frame is not correct and has following issue - 1. Number of clocks are more than 24 (=~26) - not okay 2. Your SDIN data is not latching on the clock falling edge, it's on the clock rise edge - not okay For DAC61402, SPI frame should have only 24 clocks and SDIN data should be latched/clocked on falling edge of SCLK line. Please read the detailed explanation from the DAC61402 data-sheet about the timing requirements in the sections mentioned below - 7.12 Timing Diagrams 8.5 Programming >> 8.5.1 Stand-Alone Operation Thanks, Sanjay
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Forum Post: ADS1282: Noise Floor is too large
Part Number: ADS1282 Tool/software: Hello, We are using ADS1282 and would like to estimate base line (noise floor) and having issues with output data. Hardwire configuration: ADC reference set to 5V DC AIN1+, AIN1- is connected via 121R to 2.5V reference voltage ADC clock set at 4.096MHZ Software Configuration Config 0 register is configured to 0xD9 D7 1 continuums SYNC mode D6 1 reserved D5:D3 001 64KHZ data rate Table6 page 18 D2 0 Linear phase D1: D0 01 Sinc Filter is selected Other registers left at default state When reading 32 bit data , we expecting data to be near 0 , according to the table 13 page 26 data sheet, but we are getting relatively large noise floor, please see attached scope plot. Yellow line is ADC RDY ; blue SPI CLK; magenta is SPI Data Out from ADC. Could you please advise what can be wrong? Thank you, Iouri
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Forum Post: RE: ADS1282: Noise Floor is too large
Hi louri Markin, Today is a holiday in the US, we will respond to your post later this week. Thanks for your patience -Bryan
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Forum Post: RE: ADS131M08: ADS131m08 SPI communication problems
Hi Emanuele Peruzzi , Today is a holiday in the US, we will respond to your post later this week. Thanks for your patience -Bryan
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Forum Post: RE: ADS131M02-Q1: Root cause of the offset issue
Hello Yoshikazu-san, when global-chop mode is disabled, then the period between DRDYn pin falling edges equals 1/Data rate. The data rate depends on the clock frequency and the configured OSR setting: Data rate = (f_CLK / 2) / OSR. You can also check table 8-2 in the datasheet. Regards, Joachim Wuerker
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Forum Post: RE: ADS127L11: Daisy-chain synchronization
Hi Jonas Martin, Today is a holiday in the US, we will respond to your post later this week. Thanks for your patience -Bryan
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Forum Post: RE: ADS1231: Behavior of ADC when reference voltage is absent
Hi Nikhil Folane, Today is a holiday in the US, we will respond to your post later this week. Thanks for your patience -Bryan
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Forum Post: RE: ADS1220EVM: Can't Manually install the ADS1220EVM plugin in ADCpro
Hi Timo Zellmer, Today is a holiday in the US, we will respond to your post later this week. Thanks for your patience -Bryan
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Forum Post: RE: DAC12DL3200: Biasing the outputs
Hi Charan, See attached. This spreadsheet might help for your DC coupled interface. Thanks, Rob e2e.ti.com/.../DCCoupled_5F00_DAC_2D00_AMP_5F00_Calculator.xlsx
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Forum Post: RE: ADS52J90: Analog input termination and coupling
Hello Sachin. Thanks for your response. The datasheet, from my reading of it, doesn't say anything about sampling glitches or the 2 x 50R and 6.8pF capacitors. I read this part to be talking about the 2 x 25R and 1uF VCM injection circuit because it's immediately after the sentence talking about VCM injection: The resistor and capacitor values used for coupling determines the high-pass filter corner of the input circuit; thus, these values are chosen with the frequency of interest in mind. But it could, I suppose, be talking about all the R's and C's on the input circuits. Are you able to guide me on the glitch sampling absorption circuit then? It looks to be a low-pass filter with a -3 dB point at around 460 MHz. Is this necessary for SNR/SINAD purposes, and at what frequencies? A response ASAP would be appreciated as I'm late in the design phase. Thanks!
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