Hi Tom, Customer asks what frequency ADS7253's SPI is, could you help clarify? Didn't find clear info in the DS:
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Forum Post: RE: ADS7253: SPI baudrate
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Forum Post: TSW14J50EVM: TSW14J50EVM
Part Number: TSW14J50EVM Other Parts Discussed in Thread: ADS54J60EVM I am currently using a 32 bits C example in HSDC Automation DLL examples in order to control the acquisition by a ADS54J60EVM. We have recently understood that the TSW14J50EVM was not the appropriate choice for the ADS54J60EVM. It should have been the TSW54J57EVM. Can you confirm this? Will the version of HSDC Pro have to be changed too? Also, I have received many times the same error message as you will find in the following FAQ case : https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1303566/tsw14j50evm-tsw1400-lvlib-is-missing . . The response by your engineers was to install the version 5.20 of HSDC Pro but this is what I have and it does not solve the problem though I have uninstalled and reinstalled twice. Weirdly, I have found that, by using my C application executable to connect to the board, even though it causes an error, after that I can use again the HSDC Pro and the error above does not appear. Is this error due to not using the appropriate TSW card? With the set of TSW14J50EVM and ADS54J60EVM cards, I am very far from meeting the 177E6 bits per second acquisition/saving specification. I hope that the TSW54J57EVM will do the job. Please, confirm that it is the good number to choose since we had, back in January, found TSW14J50EVM instead and, more recently, TSW14J56EVM . I look forward to reading from you at my company email. Robert Bernier Les instruments optiques du Saint-Laurent inc.
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Forum Post: RE: AFE58JD32: ADC data acquisition problem
Hi, Are you collecting the data at EVM or your system ? Are you following initialization sequence given in datasheet ?
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Forum Post: RE: ADS1278: SPI configuration
Hello Aravind, Your setup looks correct, except for the use of the /SYNC pin. SYNC functions similar to a RESET; when low, the device is in a RESET state and no conversions take place. When SYNC is taken high, there will be a delay before the first conversion data is ready, indicated by the falling edge of /DRDY. Figure 73 in the datasheet shows the behavior of /SYNC and /DRDY. The delay time before the first conversion result after /SYNC rising edge is tNDR, which is equal to 129 conversion periods. In your case, since CLK=25MHz (I assume you have a 25MHz continuous clock connected to the CLK pin 27), then a conversion period will be 1/25MHz*256=10.24us. tNDR=129*10.24=1.32 milliseconds. After /SYNC pin is taken high and tNDR time has been met, the /DRDY pin will pulse at the output data rate. In your configuration, this will be 97.656ksps. Your processor needs to either poll the /DRDY pin or monitor with an interrupt, and look for the /DRDY falling edge. At this time, you can then clock the data using SCLK out of the device. If you do not see any activity on the /DRDY pin, then you have a hardware problem. I suggest checking all supply voltages, and verify you have a continuous 25MHz clock present on the CLK pin. The voltage levels of this clock should be equal to the IOVDD supply voltage. Regards, Keith Nicholas Precision ADC Applications
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Forum Post: AFE4950: Maximum Channels that can be Used Simultaneously
Part Number: AFE4950 The datasheet mentions that the AFE4950 can drive up to 8 LEDs, 4 photodiodes, and 2 ECG electrodes. I wanted to ask whether using all 8 LED and/or 4 photodiode channels will result in any compromise on the operation, usability, or functionality of the electrode channels on the sensor. In other words, to what extent can I drive all the LEDs and photodiodes at the same time such that I can still achieve optimal functionality from the electrode channels, or are these drivers independent?
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Forum Post: ADS1298R: Issue with ADS1298R Lead 3 and AVL Signal Discrepancy
Part Number: ADS1298R Dear TI Support Team, I hope this message finds you well. I am writing to bring to your attention an issue I've encountered with the ADS1298R. We are using custom hardware based on the design of the development kit; the signals collected from Lead 3 and AVL do not match those generated by the simulator. (Please find attached an Excel file.) Could you please investigate this matter and provide guidance on how to resolve it? Additionally, if there are any known issues or potential solutions related to this problem, I would greatly appreciate any insights or recommendations you can offer. Please find the schematic attached. Thank you for your attention to this matter. I look forward to your prompt response and assistance in resolving this issue. Best regards, Thuan Le e2e.ti.com/.../ECG-12-Channel-Mainboard-V3.1.pdf e2e.ti.com/.../ECG-Testing-Release-2.xlsx
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Forum Post: TSW1418EVM: firmware for ADC3683EVM capture
Part Number: TSW1418EVM Other Parts Discussed in Thread: ADC3683EVM , Is it possible to receive the source for capturing data from ADC3683EVM via the TSW1418EVM? We have both parts and everything is working with the GUIs. It would be helpful to have example capture code to explore additional features. I'm especially interested in the 20-bit output mode after complex down-conversion and decimation. Thanks!
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Forum Post: RE: ADS7830: Internal Voltage Reference Drop after I2C detect command
Hi Matt, It looks like the original write to 0x48 activated the write to the ADS7830 and then the following 0x49 was used as the command bit. What happened after the ACK to address 0x4B?
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Forum Post: DAC12DL3200: DAC not updating from LVDS
Part Number: DAC12DL3200 Hello, We are using the DAC12DL3200 in a radio transmitter application and are having trouble configuring it. We can use the SPIDAC register to update the output, but when configured for LVDS we get no change in output (except by changing the SPI coarse gain control). Can you please review our register settings and let us know what we may be doing wrong? The datasheet is a little ambiguous on the configuration details. thank you, joel p.s. we were asked by our FAE to post this in the processor forum const uint32_t DAC_REGS[5] = { 0x101f1, 0x16033, 0x17000, 0x10000, 0x2203, 0x18000, }; e2e.ti.com/.../0000313298_2D00_B01_2D00_R1.RC4_2D00_schematics_2800_dac_5F00_no_5F00_titleblock_2900_.pdf
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Forum Post: RE: ADS5407: DACLK/DBCLK outputs are not generating
Hi Sangam, I am going to close this post. It can be reopened if needed. Best regards, Drew
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Forum Post: RE: DAC63204EVM: EVM GUI issue
Hi Pooja, The GUI is in demo mode in your screenshot. The GUI is not sending the DAC any commands while in demo mode. Can you uncheck the demo mode checkbox at the top right? When you are not in demo mode, you can select read all at the top of the low level page to get the register settings that are currently in the device. To see a DAC output you should write 0x1249 to register 0x1F to power on . Write 0x0800 to register 0x03, 0x09, 0x0F, 0x15 to set the gain. And then write the data to register 0x19, 0x1A, 0x1B, and 0x1C. Best, Katlynne Jones
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Forum Post: RE: DAC81416EVM: Stability of voltages
Hi Jesus, I am going to consolidate your posts to one thread. Please refer to: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1354910/dac8814evm-stability-of-voltages Best, Katlynne Jones
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Forum Post: RE: DAC8562TEVM: Stability f voltages
Hi Jesus, I am going to consolidate your posts to one thread. Please refer to: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1354910/dac8814evm-stability-of-voltages Best, Katlynne Jones
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Forum Post: RE: ADS7066: Auto Sequence Mode Reading data frame size? 12bit? 16bit?
Hi Joe, Thanks for clarifying. Those register settings and the initialization sequence look correct. Referring to Table 7-4, you may still need to send 24 SCLKs, even though CRC, averaging, and STATUS words are all disabled. Can you try extending the frame to send 3 bytes of 0x00 on SDI? I might also recommend enabling the channel ID status just for now to ensure that the internal multiplexer is cycling through the channels as expected. Can you share a schematic so we can review what all is connected to the I/O lines? Regards, Ryan
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Forum Post: RE: ADS8681: Intermittent Erroneous ADC Readings
Hi Rafaele, Thanks for clarifying. Would you be able to swap the two devices and see if the issue follows the IC? Regards, Ryan
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Forum Post: RE: DAC8814EVM: Stability of voltages
Hi Jesus, I am going to consolidate your posts to one thread. The DAC8562T does not have a ±10V range. The DAC81416 and DAC8814 do both have a ±10V range. The DAC8814 is an MDAC which means it requires an output buffer. For a bipolar output you'd need to use the following configuration: The only change in the output for the DAC8814 and DAC81416 once you set the output voltage will be due to any drift in the gain error, offset error, or reference voltage. The DAC81416 has an internal reference, so the drift spec is shown in the datasheet along with the gain and offset error specs. The DAC8814 requires an external reference, so the drift will be dependent on the drift of the reference you choose. Similarly, any drift specs of the external output buffer you use will affect the voltage drift. Best, Katlynne
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Forum Post: RE: TSW14J58EVM: AFE7950EVM Program configuration and waveform generation
Hi Zhu, The ddcFactor and ducFactor are the decimation and interpolation factors for the ADCs and DACs. The sampling rates are given in the FadcRx, FadcFb, and Fdac parameters. The two numbers in the sysParams.txNco0 parameter are for the two bands. In the AFE each channel can support single or dual band and each band will have its own NCO. If using single band then the second value will not be used and can be ignored. I recommend referencing the AFE79xx_Configuration_Guide, which is available in the AFE79xx secure folder, for additional information on the AFE parameters as this document will cover all of the parameters you are referencing. Regards, David Chaparro
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Forum Post: ADS1278EVM-PDK: ADS1278EVM-PDK-SW Plugin Availability
Part Number: ADS1278EVM-PDK I have two of the the ADS1278EVM-PDK evaluation modules (version 1/with MMB0) and the plugin is no longer available for download from the website. Can you point me to an alternate link to download the ADS1278EVM-PDK-SW plugin?
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Forum Post: RE: ADS1278EVM-PDK: ADS1278EVM-PDK-SW Plugin Availability
Found the link buried in another thread. https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1238092/ads1278-sp-software-issue-with-evaluation-board Thank you Christopher Hall
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Forum Post: RE: ADS1235: Grounding Thermal Pad with bipolar power
Hi Philip Ouellette, There is a possibility that there can be higher leakage current at higher temperature when the thermal pad is connected to DGND instead of AVSS in a bipolar configuration. The recommended option would be to connect the thermal pad to AVSS -Bryan
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