I have check the point 1 and point 2, which are the same as the following. 1. Check SD card on bottom of SDCC board, also check SD card on the bottom of ADS8688EVM. These two of them can not be mixed to use. 2. Check the LED lights(D2,D5) flashing situation on SDCC board. But the voltage on TP14 is 3.2V, TP16 1.1V, TP 17 0V, the are not right. So what may cause this problem happened?

I would like to add that we are not using the internal digital filters of the ADS1281 . We are using our own digital filter. That is also why we wanted to send you the original bit stream showing that the tones are there before the digital filter.

Part Number: PCM1796 Tool/software: Linux Hi there! I'm new with PCM1796 DAC and have some issues to work with it. I've defined my dts in order to enable I2C working with it, is connected to the power supply but i can't detect the device when use i2cdetect... I've read in the datasheet about an internal reset if not detects 1024 system clock cycles. Currently, is not connected to the I2S bus so no system clock is available. Could be this the problem to get it working?? In addition, is there any ALSA driver available for this codec? Best Regards!

After we change the Reset timing. this issue is resolved. another question, for the register 46: We need change it to 8110 to get the right SDR output CLKC=12*ADCLK, if set to 8210 as datasheet the CLKC=14*ADCLK. After we check ADS5294 as below. So the ADS5287 register 46 table bit: D9 is not match for 10bit setting, could you give some comment. Thanks.

Part Number: TLV320AIC3268 In the design, the plan is to drive the 8ohms 3W speaker. Since the TLV320AIC3268 can drive max of 1.45W, the external Class D (TPA3132D2RHBT) is being used. The external class D amplifier has a minimum gain of 26db. And as per the data sheet of TLV320AIC3268 , the minimum gain is 6db and it cannot be configured with a unity gain. So for this application, can we use the receiver amplifier (RECP &RECM) to drive the external class D AMP and speaker?, the reason is the receiver amplifier (RECP &RECM) can be configured with a unity gain using the register setting

Part Number: ADS131A04 Hello! I am using MSP432 to communicate with ADS131A04 ADC using 32 bit words, at 1MHz SPI clock. The problem is that after I enable the ADC channels (in 0x0F register) I get STAT1 = 0x2220 (indicating a fault with SPI), and when reading STAT_S I get 0x2501 which is F_FRAME fault. I've tried clearing the bit by reading STAT_S many times, but it will not clear. The bit will clear only after if I disable the ADC channels and read STAT_S. I mention that I am using the same read/write functions, so there should not be any issues related to insufficient SCLKs. Also, even when F_FRAME is set, I am able to successfully read/write the ADC's registers. I've attached the logic analyzer capture so you can have a look (you need Saleae Logic software to open it; it can be downloaded for free). Is this normal behavior? If not, why is F_FRAME set only when the ADC channels are enabled? (Please visit the site to view this file)

Part Number: DAC8822 Dear Team, What is the VIH min value digital data-lines in DAC8822 when VDD=5V. From the datasheet i found Vih min of control signals are 2.4, so i planned to give from 3.3V bank of FPGA. here i wanted to know control signal means A0,A1,WR#,RS#,LDAC and RSTSEL only right. Regards, Prasanna G

Hi Christian, How is the M1 pin configured on your ADS131A04 device? What are the register contents of the D_SYS_CFG register? In your screen capture, I suspect the 'SPI-ENABLE' line is connected to the Chip Select pin of the ADS131A04 , is that right? If you review section 9.5, a data frame consists of multiple data words which are 'framed' by chip select and it looks like you are taking /CS high between each data word. Can you hold /CS low through the entire data frame transmission and let us know if that clears the F_FRAME error?

Hi Iven, The I2C timeout should be 35mS MAX. Section 9.2.2.2.1 is referring to the power on reset functionality of the device which will be dependent to some extent of the ramp of the power supply as well as the amount of capacitance on the bus.

Hello, I have tried the 400ohm internal as an mux option. This result in small changes on the offset. The noise is equal. Could I use this mux setting for any purpose? I have tried the offset calib function command without this doing any changes to the offset calib reg. So in the continuous work I will find correct values and write them directly to the regsters. Hopefully I get this calib func to work later on. I will also use the HW with shorted R72 on the ref output since I should have had individual filters for each ADS. At the moment I have a 100uF on the outside. And hopefully this is stable enough. Br Leif G

Thanks Tom.

Hello Tom, M1 = 1, so I use 32 bit words. D_SYS_CFG = 0x3C (default value). I see in D_SYS_CFG that FIXED = 0 meaning "Device words per data frame depends on whether the CRC and ADCs are enabled". This somewhat explains why the behavior appears only when ADCs are enabled, however it should not affect me, because CRC is disabled. Do I need to write 5 bytes after enabling the ADCs when checking the register value after writing it? The ADC CS (pin 23) is connected to the MSP432 CS pin. Currently, every data frame is framed by CS (i.e., take CS low, transmit 4 bytes, take CS high). In this case, shouldn't the error appear earlier and not only after I enable the ADCs? Are you suggesting to take CS low, transmit 8 bytes and then take CS high?

Part Number: ADS122U04EVM There's an error in the BOM for the ADS122U04 EVM board in the May 2017 user's guide on page 32... If you look below the 0.01uF and 0.1uF capacitors have the exact same TDK part number despite completely different specs. I couldn't find TDK capacitor with those specs so I have no idea what the correct part number should be.

Part Number: DAC8775EVM Hello experts! I need VHDL code of SPI to check the output of the DAC8775EVM , I am unable to get the output with my spi. Kindly share code with me, it would be very helpful for me. Thanks.

sir, i am appending the driver code which i am using . /* * ALSA SoC TLV320AIC3X codec driver * * Author: Vladimir Barinov, * Copyright: (C) 2007 MontaVista Software, Inc., * * Based on sound/soc/codecs/wm8753.c by Liam Girdwood * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * Notes: * The AIC3X is a driver for a low power stereo audio * codecs aic31, aic32, aic33, aic3007. * * It supports full aic33 codec functionality. * The compatibility with aic32, aic31 and aic3007 is as follows: * aic32/aic3007 | aic31 * --------------------------------------- * MONO_LOUT -> N/A | MONO_LOUT -> N/A * | IN1L -> LINE1L * | IN1R -> LINE1R * | IN2L -> LINE2L * | IN2R -> LINE2R * | MIC3L/R -> N/A * truncated internal functionality in * accordance with documentation * --------------------------------------- * * Hence the machine layer should disable unsupported inputs/outputs by * snd_soc_dapm_disable_pin(codec, "MONO_LOUT"), etc. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "tlv320aic3x.h" #define AIC3X_NUM_SUPPLIES 4 static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = { "IOVDD", /* I/O Voltage */ "DVDD", /* Digital Core Voltage */ "AVDD", /* Analog DAC Voltage */ "DRVDD", /* ADC Analog and Output Driver Voltage */ }; static LIST_HEAD(reset_list); struct aic3x_priv; struct aic3x_disable_nb { struct notifier_block nb; struct aic3x_priv *aic3x; }; /* codec private data */ struct aic3x_priv { struct snd_soc_codec *codec; struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES]; struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES]; enum snd_soc_control_type control_type; struct aic3x_setup_data *setup; unsigned int sysclk; struct list_head list; int master; int gpio_reset; int power; #define AIC3X_MODEL_3X 0 #define AIC3X_MODEL_33 1 #define AIC3X_MODEL_3007 2 u16 model; }; /* * AIC3X register cache * We can't read the AIC3X register space when we are * using 2 wire for device control, so we cache them instead. * There is no point in caching the reset register */ static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = { 0x00, 0x00, 0x00, 0x10, /* 0 */ 0x04, 0x00, 0x00, 0x00, /* 4 */ 0x00, 0x00, 0x00, 0x01, /* 8 */ 0x00, 0x00, 0x00, 0x80, /* 12 */ 0x80, 0xff, 0xff, 0x78, /* 16 */ 0x78, 0x78, 0x78, 0x78, /* 20 */ 0x78, 0x00, 0x00, 0xfe, /* 24 */ 0x00, 0x00, 0xfe, 0x00, /* 28 */ 0x18, 0x18, 0x00, 0x00, /* 32 */ 0x00, 0x00, 0x00, 0x00, /* 36 */ 0x00, 0x00, 0x00, 0x80, /* 40 */ 0x80, 0x00, 0x00, 0x00, /* 44 */ 0x00, 0x00, 0x00, 0x04, /* 48 */ 0x00, 0x00, 0x00, 0x00, /* 52 */ 0x00, 0x00, 0x04, 0x00, /* 56 */ 0x00, 0x00, 0x00, 0x00, /* 60 */ 0x00, 0x04, 0x00, 0x00, /* 64 */ 0x00, 0x00, 0x00, 0x00, /* 68 */ 0x04, 0x00, 0x00, 0x00, /* 72 */ 0x00, 0x00, 0x00, 0x00, /* 76 */ 0x00, 0x00, 0x00, 0x00, /* 80 */ 0x00, 0x00, 0x00, 0x00, /* 84 */ 0x00, 0x00, 0x00, 0x00, /* 88 */ 0x00, 0x00, 0x00, 0x00, /* 92 */ 0x00, 0x00, 0x00, 0x00, /* 96 */ 0x00, 0x00, 0x02, /* 100 */ }; /* * read from the aic3x register space. Only use for this function is if * wanting to read volatile bits from those registers that has both read-only * and read/write bits. All other cases should use snd_soc_read. */ static int aic3x_read(struct snd_soc_codec *codec, unsigned int reg, u8 *value) { u8 *cache = codec->reg_cache; if (codec->cache_only) return -EINVAL; if (reg >= AIC3X_CACHEREGNUM) return -1; codec->cache_bypass = 1; *value = snd_soc_read(codec, reg); printk("register= %d value=%d \n",reg,*value); codec->cache_bypass = 0; cache[reg] = *value; return 0; } #define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \ { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ .info = snd_soc_info_volsw, \ .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw_aic3x, \ .private_value = SOC_SINGLE_VALUE(reg, shift, mask, invert) } /* * All input lines are connected when !0xf and disconnected with 0xf bit field, * so we have to use specific dapm_put call for input mixer */ static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol); struct snd_soc_dapm_widget *widget = wlist->widgets[0]; struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; unsigned int reg = mc->reg; unsigned int shift = mc->shift; int max = mc->max; unsigned int mask = (1 invert; unsigned short val, val_mask; int ret; struct snd_soc_dapm_path *path; int found = 0; val = (ucontrol->value.integer.value[0] & mask); mask = 0xf; if (val) val = mask; if (invert) val = mask - val; val_mask = mask codec->mutex); if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) { /* find dapm widget path assoc with kcontrol */ list_for_each_entry(path, &widget->dapm->card->paths, list) { if (path->kcontrol != kcontrol) continue; /* found, now check type */ found = 1; if (val) /* new connection */ path->connect = invert ? 0 : 1; else /* old connection must be powered down */ path->connect = invert ? 1 : 0; dapm_mark_dirty(path->source, "tlv320aic3x source"); dapm_mark_dirty(path->sink, "tlv320aic3x sink"); break; } if (found) snd_soc_dapm_sync(widget->dapm); } ret = snd_soc_update_bits(widget->codec, reg, val_mask, val); mutex_unlock(&widget->codec->mutex); return ret; } static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" }; static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" }; static const char *aic3x_left_hpcom_mux[] = { "differential of HPLOUT", "constant VCM", "single-ended" }; static const char *aic3x_right_hpcom_mux[] = { "differential of HPROUT", "constant VCM", "single-ended", "differential of HPLCOM", "external feedback" }; static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" }; static const char *aic3x_adc_hpf[] = { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" }; #define LDAC_ENUM 0 #define RDAC_ENUM 1 #define LHPCOM_ENUM 2 #define RHPCOM_ENUM 3 #define LINE1L_2_L_ENUM 4 #define LINE1L_2_R_ENUM 5 #define LINE1R_2_L_ENUM 6 #define LINE1R_2_R_ENUM 7 #define LINE2L_ENUM 8 #define LINE2R_ENUM 9 #define ADC_HPF_ENUM 10 static const struct soc_enum aic3x_enum[] = { SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux), SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux), SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux), SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux), SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux), SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux), SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf), }; /* * DAC digital volumes. From -63.5 to 0 dB in 0.5 dB steps */ static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0); /* ADC PGA gain volumes. From 0 to 59.5 dB in 0.5 dB steps */ static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0); /* * Output stage volumes. From -78.3 to 0 dB. Muted below -78.3 dB. * Step size is approximately 0.5 dB over most of the scale but increasing * near the very low levels. * Define dB scale so that it is mostly correct for range about -55 to 0 dB * but having increasing dB difference below that (and where it doesn't count * so much). This setting shows -50 dB (actual is -50.3 dB) for register * value 100 and -58.5 dB (actual is -78.3 dB) for register value 117. */ static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1); static const struct snd_kcontrol_new aic3x_snd_controls[] = { /* Output */ SOC_DOUBLE_R_TLV("PCM Playback Volume", LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv), /* * Output controls that map to output mixer switches. Note these are * only for swapped L-to-R and R-to-L routes. See below stereo controls * for direct L-to-L and R-to-R routes. */ SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume", LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume", PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume", DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume", LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume", PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume", DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume", LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume", PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume", DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume", LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume", PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume", DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume", LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume", PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume", DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume", LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume", PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume", DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), /* Stereo output controls for direct L-to-L and R-to-R routes */ SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume", LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_DOUBLE_R_TLV("Line PGA Bypass Volume", PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_DOUBLE_R_TLV("Line DAC Playback Volume", DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume", LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume", PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_DOUBLE_R_TLV("Mono DAC Playback Volume", DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL, 0, 118, 1, output_stage_tlv), SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume", LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), SOC_DOUBLE_R_TLV("HP PGA Bypass Volume", PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), SOC_DOUBLE_R_TLV("HP DAC Playback Volume", DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv), SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume", LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume", PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume", DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv), /* Output pin mute controls */ SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3, 0x01, 0), SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0), SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3, 0x01, 0), SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3, 0x01, 0), /* * Note: enable Automatic input Gain Controller with care. It can * adjust PGA to max value when ADC is on and will never go back. */ SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0), /* Input */ SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL, 0, 119, 0, adc_tlv), SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1), SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]), }; /* * Class-D amplifier gain. From 0 to 18 dB in 6 dB steps */ static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0); static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl = SOC_DOUBLE_TLV("Class-D Amplifier Gain", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv); /* Left DAC Mux */ static const struct snd_kcontrol_new aic3x_left_dac_mux_controls = SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]); /* Right DAC Mux */ static const struct snd_kcontrol_new aic3x_right_dac_mux_controls = SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]); /* Left HPCOM Mux */ static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls = SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]); /* Right HPCOM Mux */ static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls = SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]); /* Left Line Mixer */ static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = { SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0), }; /* Right Line Mixer */ static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = { SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0), }; /* Mono Mixer */ static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = { SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0), }; /* Left HP Mixer */ static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = { SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0), }; /* Right HP Mixer */ static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = { SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0), }; /* Left HPCOM Mixer */ static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = { SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0), }; /* Right HPCOM Mixer */ static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = { SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0), SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0), }; /* Left PGA Mixer */ static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = { SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1), SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1), SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1), SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1), SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1), }; /* Right PGA Mixer */ static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = { SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1), SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1), SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1), SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1), SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1), }; /* Left Line1 Mux */ static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls = SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]); static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls = SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]); /* Right Line1 Mux */ static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls = SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]); static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls = SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]); /* Left Line2 Mux */ static const struct snd_kcontrol_new aic3x_left_line2_mux_controls = SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]); /* Right Line2 Mux */ static const struct snd_kcontrol_new aic3x_right_line2_mux_controls = SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]); static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = { /* Left DAC to Left Outputs */ SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0), SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0, &aic3x_left_dac_mux_controls), SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0, &aic3x_left_hpcom_mux_controls), SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0), /* Right DAC to Right Outputs */ SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0), SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0, &aic3x_right_dac_mux_controls), SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0, &aic3x_right_hpcom_mux_controls), SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0), SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0), /* Mono Output */ SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0), /* Inputs to Left ADC */ SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0), SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0, &aic3x_left_pga_mixer_controls[0], ARRAY_SIZE(aic3x_left_pga_mixer_controls)), SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0, &aic3x_left_line1l_mux_controls), SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0, &aic3x_left_line1r_mux_controls), SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0, &aic3x_left_line2_mux_controls), /* Inputs to Right ADC */ SND_SOC_DAPM_ADC("Right ADC", "Right Capture", LINE1R_2_RADC_CTRL, 2, 0), SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0, &aic3x_right_pga_mixer_controls[0], ARRAY_SIZE(aic3x_right_pga_mixer_controls)), SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0, &aic3x_right_line1l_mux_controls), SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0, &aic3x_right_line1r_mux_controls), SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0, &aic3x_right_line2_mux_controls), /* * Not a real mic bias widget but similar function. This is for dynamic * control of GPIO1 digital mic modulator clock output function when * using digital mic. */ SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk", AIC3X_GPIO1_REG, 4, 0xf, AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK, AIC3X_GPIO1_FUNC_DISABLED), /* * Also similar function like mic bias. Selects digital mic with * configurable oversampling rate instead of ADC converter. */ SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128", AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0), SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64", AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0), SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32", AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0), /* Mic Bias */ SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2V", MICBIAS_CTRL, 6, 3, 1, 0), SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias 2.5V", MICBIAS_CTRL, 6, 3, 2, 0), SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "Mic Bias AVDD", MICBIAS_CTRL, 6, 3, 3, 0), /* Output mixers */ SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0, &aic3x_left_line_mixer_controls[0], ARRAY_SIZE(aic3x_left_line_mixer_controls)), SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0, &aic3x_right_line_mixer_controls[0], ARRAY_SIZE(aic3x_right_line_mixer_controls)), SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0, &aic3x_mono_mixer_controls[0], ARRAY_SIZE(aic3x_mono_mixer_controls)), SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, &aic3x_left_hp_mixer_controls[0], ARRAY_SIZE(aic3x_left_hp_mixer_controls)), SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, &aic3x_right_hp_mixer_controls[0], ARRAY_SIZE(aic3x_right_hp_mixer_controls)), SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0, &aic3x_left_hpcom_mixer_controls[0], ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)), SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0, &aic3x_right_hpcom_mixer_controls[0], ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)), SND_SOC_DAPM_OUTPUT("LLOUT"), SND_SOC_DAPM_OUTPUT("RLOUT"), SND_SOC_DAPM_OUTPUT("MONO_LOUT"), SND_SOC_DAPM_OUTPUT("HPLOUT"), SND_SOC_DAPM_OUTPUT("HPROUT"), SND_SOC_DAPM_OUTPUT("HPLCOM"), SND_SOC_DAPM_OUTPUT("HPRCOM"), SND_SOC_DAPM_INPUT("MIC3L"), SND_SOC_DAPM_INPUT("MIC3R"), SND_SOC_DAPM_INPUT("LINE1L"), SND_SOC_DAPM_INPUT("LINE1R"), SND_SOC_DAPM_INPUT("LINE2L"), SND_SOC_DAPM_INPUT("LINE2R"), /* * Virtual output pin to detection block inside codec. This can be * used to keep codec bias on if gpio or detection features are needed. * Force pin on or construct a path with an input jack and mic bias * widgets. */ SND_SOC_DAPM_OUTPUT("Detection"), }; static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = { /* Class-D outputs */ SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0), SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0), SND_SOC_DAPM_OUTPUT("SPOP"), SND_SOC_DAPM_OUTPUT("SPOM"), }; static const struct snd_soc_dapm_route intercon[] = { /* Left Input */ {"Left Line1L Mux", "single-ended", "LINE1L"}, {"Left Line1L Mux", "differential", "LINE1L"}, {"Left Line2L Mux", "single-ended", "LINE2L"}, {"Left Line2L Mux", "differential", "LINE2L"}, {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"}, {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"}, {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"}, {"Left PGA Mixer", "Mic3L Switch", "MIC3L"}, {"Left PGA Mixer", "Mic3R Switch", "MIC3R"}, {"Left ADC", NULL, "Left PGA Mixer"}, {"Left ADC", NULL, "GPIO1 dmic modclk"}, /* Right Input */ {"Right Line1R Mux", "single-ended", "LINE1R"}, {"Right Line1R Mux", "differential", "LINE1R"}, {"Right Line2R Mux", "single-ended", "LINE2R"}, {"Right Line2R Mux", "differential", "LINE2R"}, {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"}, {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"}, {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"}, {"Right PGA Mixer", "Mic3L Switch", "MIC3L"}, {"Right PGA Mixer", "Mic3R Switch", "MIC3R"}, {"Right ADC", NULL, "Right PGA Mixer"}, {"Right ADC", NULL, "GPIO1 dmic modclk"}, /* * Logical path between digital mic enable and GPIO1 modulator clock * output function */ {"GPIO1 dmic modclk", NULL, "DMic Rate 128"}, {"GPIO1 dmic modclk", NULL, "DMic Rate 64"}, {"GPIO1 dmic modclk", NULL, "DMic Rate 32"}, /* Left DAC Output */ {"Left DAC Mux", "DAC_L1", "Left DAC"}, {"Left DAC Mux", "DAC_L2", "Left DAC"}, {"Left DAC Mux", "DAC_L3", "Left DAC"}, /* Right DAC Output */ {"Right DAC Mux", "DAC_R1", "Right DAC"}, {"Right DAC Mux", "DAC_R2", "Right DAC"}, {"Right DAC Mux", "DAC_R3", "Right DAC"}, /* Left Line Output */ {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"}, {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"}, {"Left Line Out", NULL, "Left Line Mixer"}, {"Left Line Out", NULL, "Left DAC Mux"}, {"LLOUT", NULL, "Left Line Out"}, /* Right Line Output */ {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"}, {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"}, {"Right Line Out", NULL, "Right Line Mixer"}, {"Right Line Out", NULL, "Right DAC Mux"}, {"RLOUT", NULL, "Right Line Out"}, /* Mono Output */ {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"}, {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"}, {"Mono Out", NULL, "Mono Mixer"}, {"MONO_LOUT", NULL, "Mono Out"}, /* Left HP Output */ {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"}, {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"}, {"Left HP Out", NULL, "Left HP Mixer"}, {"Left HP Out", NULL, "Left DAC Mux"}, {"HPLOUT", NULL, "Left HP Out"}, /* Right HP Output */ {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"}, {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"}, {"Right HP Out", NULL, "Right HP Mixer"}, {"Right HP Out", NULL, "Right DAC Mux"}, {"HPROUT", NULL, "Right HP Out"}, /* Left HPCOM Output */ {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"}, {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"}, {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"}, {"Left HP Com", NULL, "Left HPCOM Mux"}, {"HPLCOM", NULL, "Left HP Com"}, /* Right HPCOM Output */ {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"}, {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"}, {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"}, {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"}, {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"}, {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"}, {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"}, {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"}, {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"}, {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"}, {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"}, {"Right HP Com", NULL, "Right HPCOM Mux"}, {"HPRCOM", NULL, "Right HP Com"}, }; static const struct snd_soc_dapm_route intercon_3007[] = { /* Class-D outputs */ {"Left Class-D Out", NULL, "Left Line Out"}, {"Right Class-D Out", NULL, "Left Line Out"}, {"SPOP", NULL, "Left Class-D Out"}, {"SPOM", NULL, "Right Class-D Out"}, }; static int aic3x_add_widgets(struct snd_soc_codec *codec) { struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); struct snd_soc_dapm_context *dapm = &codec->dapm; snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets, ARRAY_SIZE(aic3x_dapm_widgets)); /* set up audio path interconnects */ snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon)); if (aic3x->model == AIC3X_MODEL_3007) { snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets, ARRAY_SIZE(aic3007_dapm_widgets)); snd_soc_dapm_add_routes(dapm, intercon_3007, ARRAY_SIZE(intercon_3007)); } return 0; } static int aic3x_hw_params(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) { struct snd_soc_pcm_runtime *rtd = substream->private_data; struct snd_soc_codec *codec =rtd->codec; struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0; u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1; u16 d, pll_d = 1; u8 reg; int clk; /* select data word length */ data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 sysclk / (128 * pll_q) == fsref) { bypass_pll = 1; break; } if (bypass_pll) { pll_q &= 0xf; snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q = 64000) data |= DUAL_RATE_MODE; snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data); /* codec sample rate select */ data = (fsref * 20) / params_rate(params); if (params_rate(params) sysclk / 1000); for (r = 1; r 11) continue; /* do not use codec_clk here since we'd loose precision */ d = ((2048 * p * fsref) - j * aic3x->sysclk) * 100 / (aic3x->sysclk/100); clk = (10000 * j + d) / (10 * p); /* check whether this values get closer than the best * ones we had before */ if (abs(codec_clk - clk) > 6) codec; u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON; u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON; if (mute) { snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON); snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON); } else { snd_soc_write(codec, LDAC_VOL, ldac_reg); snd_soc_write(codec, RDAC_VOL, rdac_reg); } return 0; } static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai, int clk_id, unsigned int freq, int dir) { struct snd_soc_codec *codec = codec_dai->codec; struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); aic3x->sysclk = freq; return 0; } static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) { struct snd_soc_codec *codec = codec_dai->codec; struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); u8 iface_areg, iface_breg; int delay = 0; iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f; iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f; /* set master/slave audio interface */ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { case SND_SOC_DAIFMT_CBM_CFM: aic3x->master = 1; iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER; break; case SND_SOC_DAIFMT_CBS_CFS: aic3x->master = 0; iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER); break; default: return -EINVAL; } /* * match both interface format and signal polarities since they * are fixed */ switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK)) { case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF): break; case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF): delay = 1; case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF): iface_breg |= (0x01 reg_cache; /* * There is no need to cache writes to undocumented page 0xD but * respective page 0 register cache entries must be preserved */ tmp1 = cache[0xD]; tmp2 = cache[0x8]; /* Class-D speaker driver init; datasheet p. 46 */ snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D); snd_soc_write(codec, 0xD, 0x0D); snd_soc_write(codec, 0x8, 0x5C); snd_soc_write(codec, 0x8, 0x5D); snd_soc_write(codec, 0x8, 0x5C); snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00); cache[0xD] = tmp1; cache[0x8] = tmp2; return 0; } static int aic3x_regulator_event(struct notifier_block *nb, unsigned long event, void *data) { struct aic3x_disable_nb *disable_nb = container_of(nb, struct aic3x_disable_nb, nb); struct aic3x_priv *aic3x = disable_nb->aic3x; if (event & REGULATOR_EVENT_DISABLE) { /* * Put codec to reset and require cache sync as at least one * of the supplies was disabled */ if (gpio_is_valid(aic3x->gpio_reset)) gpio_set_value(aic3x->gpio_reset, 0); aic3x->codec->cache_sync = 1; } return 0; } static int aic3x_set_power(struct snd_soc_codec *codec, int power) { struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); int i, ret; u8 *cache = codec->reg_cache; if (power) { ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); if (ret) goto out; aic3x->power = 1; /* * Reset release and cache sync is necessary only if some * supply was off or if there were cached writes */ if (!codec->cache_sync) goto out; if (gpio_is_valid(aic3x->gpio_reset)) { udelay(1); gpio_set_value(aic3x->gpio_reset, 1); } /* Sync reg_cache with the hardware */ codec->cache_only = 0; for (i = AIC3X_SAMPLE_RATE_SEL_REG; i model == AIC3X_MODEL_3007) aic3x_init_3007(codec); codec->cache_sync = 0; } else { /* * Do soft reset to this codec instance in order to clear * possible VDD leakage currents in case the supply regulators * remain on */ snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); codec->cache_sync = 1; aic3x->power = 0; /* HW writes are needless when bias is off */ codec->cache_only = 1; ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); /* Enable cache sync if regulator disable * event is not triggerd. * ToDo : Revisit later to fix it */ codec->cache_sync = 1; } out: return ret; } static int aic3x_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); u8 reg; switch (level) { case SND_SOC_BIAS_ON: break; case SND_SOC_BIAS_PREPARE: if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY && aic3x->master) { /* enable pll */ reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG); snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg | PLL_ENABLE); } break; case SND_SOC_BIAS_STANDBY: if (!aic3x->power) aic3x_set_power(codec, 1); if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE && aic3x->master) { /* disable pll */ reg = snd_soc_read(codec, AIC3X_PLL_PROGA_REG); snd_soc_write(codec, AIC3X_PLL_PROGA_REG, reg & ~PLL_ENABLE); } break; case SND_SOC_BIAS_OFF: if (aic3x->power) aic3x_set_power(codec, 0); break; } codec->dapm.bias_level = level; return 0; } void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state) { u8 reg = gpio ? AIC3X_GPIO2_REG : AIC3X_GPIO1_REG; u8 bit = gpio ? 3: 0; u8 val = snd_soc_read(codec, reg) & ~(1 > bit) & 1; } EXPORT_SYMBOL_GPL(aic3x_get_gpio); void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect, int headset_debounce, int button_debounce) { u8 val; val = ((detect & AIC3X_HEADSET_DETECT_MASK) > 4) & 1; } EXPORT_SYMBOL_GPL(aic3x_headset_detected); int aic3x_button_pressed(struct snd_soc_codec *codec) { u8 val = 0; aic3x_read(codec, AIC3X_HEADSET_DETECT_CTRL_B, &val); return (val >> 5) & 1; } EXPORT_SYMBOL_GPL(aic3x_button_pressed); #define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 #define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) static struct snd_soc_dai_ops aic3x_dai_ops = { .hw_params = aic3x_hw_params, .digital_mute = aic3x_mute, .set_sysclk = aic3x_set_dai_sysclk, .set_fmt = aic3x_set_dai_fmt, }; static struct snd_soc_dai_driver aic3x_dai = { .name = "tlv320aic3x-hifi", .playback = { .stream_name = "Playback", .channels_min = 1, .channels_max = 2, .rates = AIC3X_RATES, .formats = AIC3X_FORMATS,}, .capture = { .stream_name = "Capture", .channels_min = 1, .channels_max = 2, .rates = AIC3X_RATES, .formats = AIC3X_FORMATS,}, .ops = &aic3x_dai_ops, .symmetric_rates = 1, }; static int aic3x_suspend(struct snd_soc_codec *codec, pm_message_t state) { aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); return 0; } static int aic3x_resume(struct snd_soc_codec *codec) { aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY); return 0; } /* * initialise the AIC3X driver * register the mixer and dsp interfaces with the kernel */ static int aic3x_init(struct snd_soc_codec *codec) { struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); int reg; snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT); snd_soc_write(codec, AIC3X_RESET, SOFT_RESET); /* DAC default volume and mute */ snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON); snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON); /* DAC to HP default volume and route to Output mixer */ snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON); snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON); snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON); snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON); /* DAC to Line Out default volume and route to Output mixer */ snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON); snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON); /* DAC to Mono Line Out default volume and route to Output mixer */ snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON); /* unmute all outputs */ reg = snd_soc_read(codec, LLOPM_CTRL); printk(" reg= %d \n",reg); snd_soc_write(codec, LLOPM_CTRL, reg | UNMUTE); reg = snd_soc_read(codec, RLOPM_CTRL); printk(" reg= %d \n",reg); snd_soc_write(codec, RLOPM_CTRL, reg | UNMUTE); reg = snd_soc_read(codec, MONOLOPM_CTRL); printk(" reg= %d \n",reg); snd_soc_write(codec, MONOLOPM_CTRL, reg | UNMUTE); reg = snd_soc_read(codec, HPLOUT_CTRL); printk(" reg= %d \n",reg); snd_soc_write(codec, HPLOUT_CTRL, reg | UNMUTE); reg = snd_soc_read(codec, HPROUT_CTRL); printk(" reg= %d \n",reg); snd_soc_write(codec, HPROUT_CTRL, reg | UNMUTE); reg = snd_soc_read(codec, HPLCOM_CTRL); printk(" reg= %d \n",reg); snd_soc_write(codec, HPLCOM_CTRL, reg | UNMUTE); reg = snd_soc_read(codec, HPRCOM_CTRL); printk(" reg= %d \n",reg); snd_soc_write(codec, HPRCOM_CTRL, reg | UNMUTE); /* ADC default volume and unmute */ snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN); snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN); /* By default route Line1 to ADC PGA mixer */ snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0); snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0); /* PGA to HP Bypass default volume, disconnect from Output Mixer */ snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL); snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL); snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL); snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL); /* PGA to Line Out default volume, disconnect from Output Mixer */ snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL); snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL); /* PGA to Mono Line Out default volume, disconnect from Output Mixer */ snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL); snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL); /* Line2 to HP Bypass default volume, disconnect from Output Mixer */ snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL); snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL); snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL); snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL); /* Line2 Line Out default volume, disconnect from Output Mixer */ snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL); snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL); /* Line2 to Mono Out default volume, disconnect from Output Mixer */ snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL); snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL); if (aic3x->model == AIC3X_MODEL_3007) { aic3x_init_3007(codec); snd_soc_write(codec, CLASSD_CTRL, 0); } return 0; } static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x) { struct aic3x_priv *a; list_for_each_entry(a, &reset_list, list) { if (gpio_is_valid(aic3x->gpio_reset) && aic3x->gpio_reset == a->gpio_reset) return true; } return false; } static int aic3x_probe(struct snd_soc_codec *codec) { struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); int ret, i; INIT_LIST_HEAD(&aic3x->list); aic3x->codec = codec; codec->dapm.idle_bias_off = 1; ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type); if (ret != 0) { dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); return ret; } if (gpio_is_valid(aic3x->gpio_reset) && !aic3x_is_shared_reset(aic3x)) { ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset"); if (ret != 0) goto err_gpio; gpio_direction_output(aic3x->gpio_reset, 0); } for (i = 0; i supplies); i++) aic3x->supplies[i].supply = aic3x_supply_names[i]; ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies), aic3x->supplies); if (ret != 0) { dev_err(codec->dev, "Failed to request supplies: %d\n", ret); goto err_get; } for (i = 0; i supplies); i++) { aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event; aic3x->disable_nb[i].aic3x = aic3x; ret = regulator_register_notifier(aic3x->supplies[i].consumer, &aic3x->disable_nb[i].nb); if (ret) { dev_err(codec->dev, "Failed to request regulator notifier: %d\n", ret); goto err_notif; } } codec->cache_only = 1; aic3x_init(codec); if (aic3x->setup) { /* setup GPIO functions */ snd_soc_write(codec, AIC3X_GPIO1_REG, (aic3x->setup->gpio_func[0] & 0xf) setup->gpio_func[1] & 0xf) model == AIC3X_MODEL_3007) snd_soc_add_controls(codec, &aic3x_classd_amp_gain_ctrl, 1); aic3x_add_widgets(codec); list_add(&aic3x->list, &reset_list); return 0; err_notif: while (i--) regulator_unregister_notifier(aic3x->supplies[i].consumer, &aic3x->disable_nb[i].nb); regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); err_get: if (gpio_is_valid(aic3x->gpio_reset) && !aic3x_is_shared_reset(aic3x)) gpio_free(aic3x->gpio_reset); err_gpio: return ret; } static int aic3x_remove(struct snd_soc_codec *codec) { struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec); int i; aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF); list_del(&aic3x->list); if (gpio_is_valid(aic3x->gpio_reset) && !aic3x_is_shared_reset(aic3x)) { gpio_set_value(aic3x->gpio_reset, 0); gpio_free(aic3x->gpio_reset); } for (i = 0; i supplies); i++) regulator_unregister_notifier(aic3x->supplies[i].consumer, &aic3x->disable_nb[i].nb); regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies); return 0; } static struct snd_soc_codec_driver soc_codec_dev_aic3x = { .set_bias_level = aic3x_set_bias_level, .reg_cache_size = ARRAY_SIZE(aic3x_reg), .reg_word_size = sizeof(u8), .reg_cache_default = aic3x_reg, .probe = aic3x_probe, .remove = aic3x_remove, .suspend = aic3x_suspend, .resume = aic3x_resume, }; #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) /* * AIC3X 2 wire address can be up to 4 devices with device addresses * 0x18, 0x19, 0x1A, 0x1B */ static const struct i2c_device_id aic3x_i2c_id[] = { { "tlv320aic3x", AIC3X_MODEL_3X }, { " tlv320aic33 ", AIC3X_MODEL_33 }, { " tlv320aic3007 ", AIC3X_MODEL_3007 }, { } }; MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id); /* * If the i2c layer weren't so broken, we could pass this kind of data * around */ static int aic3x_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { struct aic3x_pdata *pdata = i2c->dev.platform_data; struct aic3x_priv *aic3x; int ret; aic3x = kzalloc(sizeof(struct aic3x_priv), GFP_KERNEL); if (aic3x == NULL) { dev_err(&i2c->dev, "failed to create private data\n"); return -ENOMEM; } aic3x->control_type = SND_SOC_I2C; i2c_set_clientdata(i2c, aic3x); if (pdata) { aic3x->gpio_reset = pdata->gpio_reset; aic3x->setup = pdata->setup; } else { aic3x->gpio_reset = -1; } aic3x->model = id->driver_data; ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_aic3x, &aic3x_dai, 1); if (ret dev); kfree(i2c_get_clientdata(client)); return 0; } /* machine i2c codec control layer */ static struct i2c_driver aic3x_i2c_driver = { .driver = { .name = "tlv320aic3x-codec", .owner = THIS_MODULE, }, .probe = aic3x_i2c_probe, .remove = aic3x_i2c_remove, .id_table = aic3x_i2c_id, }; #endif static int __init aic3x_modinit(void) { int ret = 0; #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) ret = i2c_add_driver(&aic3x_i2c_driver); if (ret != 0) { printk(KERN_ERR "Failed to register TLV320AIC3x I2C driver: %d\n", ret); } #endif return ret; } module_init(aic3x_modinit); static void __exit aic3x_exit(void) { #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE) i2c_del_driver(&aic3x_i2c_driver); #endif } module_exit(aic3x_exit); MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver"); MODULE_AUTHOR("Vladimir Barinov"); MODULE_LICENSE("GPL");

Hi Christian, Continue reading down through section 9.5 and take a look at figure 51, when CRC is enabled, there is one additional word to the data frame. You still have to account for the enabled ADC channels though.

Hi, Sunil, Welcome to E2E, Thanks for your interest in our products!. The Class-D speaker output of the TLV320AIC3268 should not be connected directly to the TPA3132, this amplifier requires a line input, so you might use any of the available line outputs of the '3268 to drive the amplifier. The headphone outputs can be used as line outputs as well. Best Regards, -Diego Meléndez López Audio Applications Engineer

Hi, We will take a look to this issue and will get back to you as soon as possible. Best Regards, -Diego Meléndez López Audio Applications Engineer

Hi, Tony, I am attaching the codec control software for the TLV320AIC3212EVM-U . (Please visit the site to view this file) Best Regards, -Diego Meléndez López Audio Applications Engineer

Hi, Ricardo, Welcome to E2E, Thanks for your interest in our products. Is it possible for you to share the schematic?, what are the noise levels you are getting?, is it possible to share a capture of the noise?. Thanks and Best Regards, -Diego Meléndez López Audio Applications Engineer