Forum Post: DAC121S101QML-SP: Digital IO powered without power supply
Part Number: DAC121S101QML-SP Hello, Could someone say if the DAC121S101QML-SP can have its digital inputs with a dc voltage (3.3V) present without power supply on Va pin? Is there ESD protections on...
View ArticleForum Post: RE: AFE5809: Whether AC coupling required for LVDS Bit clock,...
Hi Lakshmanan, How are you? Thanks for using AFE5809 device. I will look into your SDOUT pin question. Thank you! Best regards, Chen
View ArticleForum Post: CCS: AFE4900
Tool/software: Code Composer Studio Hello, What is the PPG sample frequency of AFE4900 as follows? How to set up? uint32_t const AFE_ppg_ecg_reg_arr[][2]= { {0x00, 0x000020}, /*CONTROL0*/ {0x01,...
View ArticleForum Post: RE: ADS1299EEGFE-PDK: Differential Inputs
Hi Joao, Is the input signal being applied truly differential or single-ended? I assume that the signal is single-ended and being applied to the positive terminal. What is on the negative terminal?...
View ArticleForum Post: RE: AMC7812: seeking support for I2C communication in AMC7812
Hi Santosh, When the ADC is in auto-mode, the ICONV input acts as a toggle function. By continuously writing '1' to ICONV, you are enabling the ADC with one command and disabling it on the next...
View ArticleForum Post: RE: ADS5296A: Full scale ramp test pattern output format
Hi Chen, Very well thanks, looking forward to your answer. Thanks, Niall
View ArticleForum Post: RE: ADS124S06: ADS124S06 Protection diode
Hi Masa-san, The ADS124S06 has ESD Ratings as shown in section 7.2 of the datasheet. Although not specifically stated the ESD protection is implied on all analog and digital pins by the Absolute...
View ArticleForum Post: RE: TSW3085EVM: Change the sampling rate
Hello, the interpolation rate is located in the digital: if you are using TSW1400, there is another adjustment for FPGA clock
View ArticleForum Post: RE: DAC121S101QML-SP: Digital IO powered without power supply
Hello Matthieu, The DAC121S101QML-SP does have ESD diodes. The max current is 10 mA and the max voltage is Va + 0.3V. Violating either can impact the life of the part. Restricting the curren to below...
View ArticleForum Post: RE: ADS131E04: Propagation Delay between CLK to DRDY?
Martin, I'm not sure I understand the question. If you're asking about the delay from the conversion start to the settled data, this device uses a sinc3 filter, and takes 3 conversion cycles to settle...
View ArticleForum Post: RE: ADS1015: Configuration register writing
Oba-san, The full 16-bit word must be written to write to the configuration register. I think that the without the full 16-bit word, the write is ignored (at the minimum, the result is unknown). To...
View ArticleForum Post: RE: ADS131E04: Propagation Delay between CLK to DRDY?
Hello Joseph, thanks a lot for the swift reply. Apologies for the misunderstanding. My question was rather related to the propagation delay time between CLK and DRDY. Similar to the ones spec'ed in...
View ArticleForum Post: RE: ADS1018-Q1: Is it possible to make VDD=0V before AINx are not...
RYO-san, Generally you want to bring up VDD before applying voltage to the analog inputs. The Absolute Maximum Ratings table (on page 5 of the datasheet) shows that the analog input voltage should not...
View ArticleForum Post: RE: ADS4149: Min ENOB
Sepeedah, The ENOB min value is 10.6 bits at 170MHz. Regards, Jim
View ArticleForum Post: RE: ADS8588S: AIN_nP float input
Hi Thomas, The 2V bias is needed and created by ADS8588S ' internal AFE circuit, when your ADC's input is floating without pull-down resistor, the conversion code of this 2V will be seen on ADC's...
View ArticleForum Post: RE: TSW3085EVM: Change the sampling rate
Hi, We know that: data rate x interpolation = DAC sampling rate. Using DAC3482 _1228p8MHz_2xInt_NCO_30MHz_single_sync_source_mode the interpolation is 2x. Using the...
View ArticleForum Post: RE: ADS1115: Question about voltage divider
Bryan, I meant that the input voltage range should line up with the ADC measurement range. This goes back to something I said in my first post. For the ADS1115 , there are several input ranges that you...
View ArticleForum Post: RE: ADS8661: ADS8661 Application Note
Hi Jens, Thanks for your post, but ADS8674 's timing is a little bit different from ADS8661 'S timing. ADS8674 starts the conversion at the falling edge of /CS with following 15 during the conversion,...
View ArticleForum Post: RE: TSW3085EVM: Change the sampling rate
Hi, I think it is best that you save and send over your configuration file to review. Basicaly, besides interpolation change, you will need to change the following also for the TSW1400 evaluation with...
View ArticleForum Post: RE: ADS131A04EVM: Startup procedure
Michael, I was able to open the Saleae file and this is what I found: You'll note that the read back of the UNLOCK command is shifted by a bit. I think the problem comes in here at the fall of /CS to...
View Article