Forum Post: Irregular Clock Trigger for High Speed ADC

Hello,

I am in the process of deciding on which high-speed ADC (EVM to be more correct with an FPGA) to use for a prototype platform. Currently I lean towards the high-speed RF, >1.7Ghz Analogue BW ADC.

For the considered application the ADC must be triggered at irregular intervals. 

My question is, how is the minimum distance between samples defined in such a scenario ? Is it the ADC's maximum sampling rate ? Simply put, how quickly can I trigger the ADC ? Lets leave the FPGA part, I/O etc out of the equation at the moment.

Regards,

Evros