Giovanni,
Regarding your questions:
[quote user="Giovanni Donati"]1) I suppose that our BANK2 on the HSMC connector are quite straight forward to connect, in order to better understand: pins 41 to 98 and pins from 101 to 160 (on our HSMC) are exactly matching pins 68 to 118 and from 121 to 178 on the DAC HSMC. Is this correct?[/quote]
I believe we have the same understanding.
For example: Bank 2 of Altera board: pin 41/43 matches Bank 2 of J13B on the DAC board: pin62/64.
Bank 3 of Altera board: pin 101/103 matches bank 3 of J13C on the DAC board: pin 122/124
[quote user="Giovanni Donati"]2) Pins FPGA_CLOCKOUTP/N from the scheme are looking like meant to be input signals for the DAC Board, as the arrows are pointing in the same direction of the data pins. We have tested these pins using our FPGA Board, we have just routed the signal on this pin on the HSMC connector, to an SMA output, and we have read this signal with a oscilloscope, and we have seen that from those pins we are reading out CLK8, generated by the LMK04800.[/quote]
Yes, you may use the FPGAclk as reference clock to your FPGA. This is our implementation for TSW1400/TSW30H84EVM
[quote user="Giovanni Donati"]3) The pins on the whole first BANK of your HSMC, are not really clear to us. Are the pins FPGA_CLKOUTP2/N2 used to output C[/quote]
No, they are meant to be used in some of our GC EVMs. The FPGA_CLKout2 is used on our TSW1400 to clock the channel CD bus of the data.
[quote user="Giovanni Donati"]
4) What is the usage for all the other signals on this bank? (TXSP1, TXSP2, TXSP3, TXSP4, TXEN, PC2DAC_GPIO_1/2). Are they input or output pins?
How do they correspond to our HSMC? We are trying to match them on the schemes, but we seem not being able to find out the r
[/quote]
They are used for GC systems.
[quote user="Giovanni Donati"]5) About the clocks and the signals in order to drive the ADC, we are taking the 10 MHz reference signal generated by the board, and we are using it to construct all the signals to let the TSW30SH84EVM work. We generate a 750 MHz signal as data clock, and a 93.8 MHz signal as SYNC. About the DACCLK, is it generated automatically on the evaluation module?[/quote]
You can either configure the on-board LMK04806/08 to be in external clock mode to accept external clock source, or in synthesizer mode to generate the necessary DACCLK from the 10MHz reference. We have example GUI setting files in the default location of the TSW308x software GUI. refer to the user's guide for detail:
http://www.ti.com/litv/pdf/slau433
[quote user="Giovanni Donati"]6) In order to activate the I/Q modulator, is necessary to feed the RF LO frequency from an external signal generator in order to see the reconstructed and upconverted signal, or is it possible to bypass it and see the baseband I/Q data after the DAC chip?[/quote]
This board is meant to be used with the I/Q modulator to generate the high frequency RF spectrum. To look at the DAC output, you will need to use the DAC34SH84EVM with DAC output transformer coupled.
-Kang