Forum Post: Pipelined ADC: clock start to valid samples

I've a requirement for an ADC capable of 5msps, 10-bit (ENOB > 9.4) and control of the sample point, sounds like a SAR or sigma-delta but I wonder, can I use a pipelined ADC?

Can I hold the clock in which ever phase keeps the T/H in track mode then start clocking when I want a sample The data's going into an FPGA so it's easy to flush the pipeline but is the data that corresponds to my first clock edge (i.e. having clocked the sample through the pipeline) going to be valid? I read a paper that suggested it may be possible though some ADC's internal nodes could saturate (which nodes?).

If not, any recomendations of ADC, small (5x5 to 7x7 QFN), ENOB > 9.4, controlable sample point, 5msps, 2v5 to 3v3 digital interface, 2v analogue inputs, ideally differential?

Thanks,

Richard.