Hello Rob Thanks for the link. We downloaded and installed the version 6.0 in our machine. This has allowed us some progress: using a external signal for the Ref. Clock, we were able to make the ADC work in JMODE0, the capture is as expected. We are using a RF generator for the 1.6GHz signal for that, and another wave generator for the input signal. However, when using the internal PLL, we're still facing a similar issue as before. Here is the message that appears. We've confirm the PLL does get locked, not only via software. We also made sure that the input reference clock (50 MHz) is correct by measuring it on resistor R231. Here is a screenshot showing the PLL locked screen. We think this may be a problem with some configuration on the capture card side, since the ADC seems to be fine. Could you provide any additional insight for us?
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