Hi Yolanda, I noticed that every time there is a settings mismatch, it is related to the CLK. Additionally, all erroneous ADC readings occur when a settings mismatch is present. It seems the CLK is not being generated properly, leading to incorrect ADC readings. Correct Measurement: V = 2.96 V Incorrect Measurement: V = 0.915 V Despite this issue, I’ve managed to obtain good measurements by running tests with delays between sending the NOP condition and reading the DATA. After some experimentation, I found that a 50 µs delay works reliably and ensures the system operates correctly. Attached is the pseudocode I recently implemented. Note that I managed to reduce the initial 500 µs delay to just 1 µs, which is sufficient to ensure correct data transmission. // Select channel as MUX input SPI_ADS7066_writeSingleRegister(hADS7066, CHANNEL_SEL_ADDRESS, channel); delay_us(1); // Send no operation to let adc convert SPI_ADS7066_sendNOP(hADS7066); delay_us(50); // Read data from channel in SDO port if (WRSPI_Receive(pADS7066Desc->hSPI,(uint8_t *)&RxRawData, 3) != EMBL_OK){ SEGGER_RTT_printf(0, "ERROR: Failed to receive data\n"); Throw(EMBL_ERROR); } Thanks for the help! The ADC is now working as expected. Best regards, Jon.
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