Hi Tiziano Pigliacelli, Are you starting the SCLK period before you bring CS low? Most SPI peripherals I am aware of bring CS low and then start sending SCLKs. In this case, an SCLK period of 1us would never be an issue because there would be at least 500ns between CS low and SCLK high. So I'm not really sure what you are doing to cause this issue Also, yes, you must follow the datasheet timing requirements or it is possibly to cause issues with the communication. You violate these timing constraints at your own risk See below for why the ADC requires timing on both SCLK edges -Bryan
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