Hi peimin Wu, This is a little confusing, but the signals for 1.5mA, 1mA, 0.75mA, and 0.5mA are all consistent between the two images The other three I have circled in the image below. You can treat the graph more as the maximum = AVDD, then each previous vertical line represents AVDD-1V, AVDD-2V, etc. Since you have AVDD = 4V and the voltage at the IDAC pin is 3.3V, you have a compliance voltage of 4V-3.3V = 0.7V. You can see that all three plots for currents <0.5mA are still above the 0.99 normalized IDAC current, so you should not have any issue Of course you can always try to reduce the resistance in the IDAC path to lower the compliance voltage -Bryan
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