Hi Thorsten, I am sorry, but I do not understand you comment here: After shifting the baseline, each ADC-x core (splitting the resulting data stream into two alternating buffers) is still converting the input at ~2.5LSB std dev. But the 'center' values for each core have 'drifted' around 1-3LSB apart from each other. Also, I verified from design the resisters that were mentioned in the datasheet, were in error. There are no registers in order to change or modify the gain and offset for this ADC. I apologize for the confusion. We are correcting the datasheet to remove this section. Regards, Rob
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