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Forum Post: RE: DAC7311: Maximum current into Vout when Vdd = 0

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Hi Liam, The output will be clamped to VDD through the ESD cell. Will there really be a few milliamps flowing in this case? Usually with SMPS there is a series resistor between the DAC and SMPS for the current injection and I typically see smaller current used there. How long do you expect the SMPS to be powered on while DAC is powered off? I wouldn't recommend operating with this condition for long periods of time even with a limited current. We do have the DAC53204 which is designed for this application and the output is hi-z even when VDD is off. Best, Katlynne Jones

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