Figure 16 of the DAC5652A datasheet shows the "Single-Bus Interleaved Data Mode" timing diagram. Unfortunately, the diagram is rather terse and does not give me enough to confidently design to. A more detailed or longer diagram showing the full sequence of operations (with the internal CLKDACIQ signal) would be very helpful. My assumptions from studying the diagram are:
1> Input data is written to Data Latch A when SELECTIQ is high and to Data Latch B when SELECTIQ is low upon rising edge on WRTIQ regardless of RESETIQ sense?
2> When RESETIQ is high, the DAC outputs are never updated; only the Data Latches are updated?
3> When RESETIQ goes low, the first rising edge of CLKIQ corresponds to the first rising edge of the internal CLKDACIQ (half data rate) signal and both DAC outputs are updated 4 CLKIQ cycles (which is 2 CLKDACIQ cycles) later plus another 22ns or so for t_pd and t_s?
4> Both DAC outputs are always updated at the same time just over 4 CLKIQ cycles (which is 2 CLKDACIQ cycles) after the A and B data has been written to the data latches. In this mode, the DAC outputs are always updated at the same time (because the I and Q data outputs need to be presented at the same time).
5> In the datasheet diagram, RESETIQ is lowered just as the B Input Data is presented. Is is important that the SELECTIQ line goes low (Feed Input Data to B Input Latch) when RESETIQ is presented?
6> So the pipeline latency is 4 clock cycles, but the data can be presented at the full data rate and it shows up a latency of 4 clock cycles later at the full data rate?
Thanks, Geoff...