Hi Andrew, Oh, I see, I got it backwards. Your HW SPI was faster than SW SPI. In that case it likely isn't an issue with timing violations with the slower SW SPI. At this point I'm thinking the issue could be with the longer CS delay on the B boards as it's the only thing that is different, and you've seems to have ruled out layout issues by proving the HW SPI works on the B boards. Can you do an experiment with the HW SPI to try to mimic the longer CS delay that is there in SW SPI before the first rising edge of SPI? I'm not finding any data on any maximum timing requirements this device might have, but it's possible that there are. For example, we spec 13ns minimum setup time from the CS falling edge to the first SCLK falling edge. It's possible that there is actual some maximum time that will cause a timeout. We don't purposefully include a SPI timeout in any of our DACs that I'm aware of. If you're able to reproduce the failed communication with HW SPI by increasing the delay between CS and the first clock edge that would indicate to me that this is the issue. Best, Katlynne
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