Part Number: VSP5324-Q1 Other Parts Discussed in Thread: VSP5324 Tool/software: I have a few questions on the VSP5324 ADC. I'm trying to determine if it would be feasible to use the input clock's rising edge to capture D11 (assuming i'm doing LSB-first mode, byte-wise, on the A OUTS, and 50MSPS) Looking at the datasheet, page 9 provides a calculation for the clock propagation delay. I'm not seeing "ts" defined in any of the tables. Is it referring to "tsu", the data setup time? In figure 1, is tPDI is the same as tp in table 6.8? The definition of tp is "Input clock rising edge crossover to frame clock rising edge crossover, two-lane LVDS for 10 ≤ ƒS ≤ 80 MSPS" Will that value be the same for the input clock rising edge crossover to frame clock falling edge crossover? Looking at figure 44, there will be both instances and i'm more interesting in Worst case td is 11.8ns, which means tp is a minimum of 11.8ns no matter what ts is. 50MSPS has a 20ns period, which actually outputs 6 bits per clock period, so the bit period is like 3.33 seconds. That tells me i'd be sampling the wrong bit, but figure 44 makes it look like I could sample the rising edge and get the correct bit, so I wanted to make sure I was thinking about that correctly.
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