Just adding some info: When data error occur power on secondary side=3.48V and after LDO=3.21V and its the same voltage levels as in correct data operation. Shorting primary_power/secondary_power/clock to GND fix it (guess power-up restart). Its not latch-up but It certainly something with the CLK. Could it be some problem that CLK is logic HIGH during power up? Is it necessary to held CLK in low level during power-up by some pull down? I couldn find anything in datasheet for CLK pin, only just RC filter for trace impedance optimization. But it strange that it works on 20Mhz/15Mhz/10Mhz and not in 12.5Mhz.
↧