Dear Alexander, thanks for your quick response. The first document you send is something we encountered. We have FPGA sin3filter demodulator and send clock from FPGA and receive data at FPGA. But we have big delay between clock and data and we encountered time violation and thats why we lower the clock from 20Mhz to 10Mhz now it works fine, but we test also 12.5Mhz and we encountered something different I guess, because from the osciloscope it seems like the data from adc "skipping ones" you can see it on attached photos below. From our measurement and calculation at 12.5MHz there is no time hazard. What I do i just unpluging and plugging connector between control PCB(theres FPGA and diff.lines+connector) and measurement PCB (connector+diff.lines+ADCs) and problem sometimes occure. It even happens at power up in our converter where we used these Here you can see normal operation at 12.5Mhz(yellow=clock/green=data_from_adc): Here is problem occured (yellow=clock/green=data_from_adc):
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