Part Number: ADC12DJ5200RFEVM Other Parts Discussed in Thread: LMX2594 , Tool/software: Hi, I have an ADC12DJ5200RFEVM board that I have reworked according to the user guide for an on-board clocking configuration, i.e. using the LMX2594 output to generate the ADC clock. I am attempting to use JMODE34 with an Fs selection of 4 GHz, which I program through the GUI over USB. After configuring via the GUI I can probe the R171 & R174 site (populated after the recommended rework) using a 12 GHz RF probe and spectrum analyzer. I can see clearly the 4 GHz on both phases of the differential pair and as far as I can tell it looks normal. If I compare to the signals I see at C45 & C46 I do not see any difference in frequency or amplitude; this implies to me that the rework was successful and a proper clock is being supplied to the ADC. However in the EVM GUI, on the JESD204C tab, I do not see the "SERDES PLL LOCKED" light go green. I have seen similar posts in the TI forums, namely: https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1345009/adc12dj5200rfevm-pll-not-locking But that post does not appear to have a resolution. Has anyone been able to successfully use on-board clocking with this eval board at high-ish sample rates? Thanks, Rurik
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