Hi Tanja, My first suspicion is that you aren't switching between channels correctly. ADD[2:0] bits are read by the ADC on the 3rd, 4th, and 5th rising edges, but in the first picture sent, it seems like there is a pulse on the 6th rising edge after CS falls. From your scope captures, it's a little hard to keep track of where one conversion ends and the other begins, but I would first double check that you are setting the ADD[2:0] bits correctly. One thing you can try is grounding CH0, and bringing CH1 to AVDD, and checking to see whether you can switch between the two reliably. For debug purposes, you might try sending only 16 SCLKs at a time between CS going high. Regards, Joel
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