Hi, I have a question about the ADC3562. It's about the CLK supply timing on page 72, "9.2 Initialization Set Up," of the datasheet. I think this CLK refers to the sampling clock CLKP/M. Looking at Figure 9-6, CLK is already being supplied before a high pulse reset signal is input. Does the clock have to be supplied at the rising edge of the reset high pulse?
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