Part Number: TI-JESD204-IP Tool/software: Hello, When I integrate the IP into the Block Design in Vivado and attempt synthesis, I encounter the following errors: [Synth 8-9210] cannot access memory 'cfg_rx_lane_map_unpacked' directly [Synth 8-10976] multiple packed dimensions are not allowed in this mode of Verilog Interestingly, when I use the RTL design directly without incorporating it into the Block Design, it synthesizes successfully. Is there a way to use TI_204c IP in a Block Design and successfully synthesize it in Vivado? Any suggestions or workarounds would be greatly appreciated!
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