Part Number: DAC38J82EVM Tool/software: Hello everyone, I am using the TI_204c IP provided by Texas Instruments in my FPGA design. I have successfully created an IP using the RTL files provided, which are written in SystemVerilog . However, when I integrate the IP into the Block Design in Vivado and attempt synthesis, I encounter the following errors: [Synth 8-9210] cannot access memory 'cfg_rx_lane_map_unpacked' directly [Synth 8-10976] multiple packed dimensions are not allowed in this mode of Verilog Interestingly, when I use the RTL design directly without incorporating it into the Block Design, it synthesizes successfully. What I have tried so far: I checked whether there is an option to generate the IP files in SystemVerilog instead of Verilog, but it seems that the generated files remain in Verilog. Is there a way to use TI_204c IP in a Block Design and successfully synthesize it in Vivado? Any suggestions or workarounds would be greatly appreciated! Thanks in advance!
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