Hi Kazuya Nakai59, Answers to your questions: [quote userid="190215" url="~/support/data-converters-group/data-converters/f/data-converters-forum/1472937/ads131m08-question-about-sclk-synchronization-to-master-clock"] The following sentence is described at 8.3.5 Clocking and Power Modes section on page 22 of ADS131M08 datasheet. "For optimal performance, the modulator sampling clock must be synchronous with the serial data clock (SCLK)." Is this mandatory? They checked ADS131M08 EVM schematic. But they think that the master clock has not been synchronized with SCLK [/quote] This is not mandatory. In fact, the characterization board that we used to produce all of the datasheet parameters includes a crystal as the ADC clock source i.e. SCLK and ADC clock are not synchronized. So you should be able to achieve datasheet performance using asynchronous clocks [quote userid="190215" url="~/support/data-converters-group/data-converters/f/data-converters-forum/1472937/ads131m08-question-about-sclk-synchronization-to-master-clock"]If the master clock is not synchronized with SCLK, what is occurred? The data conversion accuracy will become worse? [/quote] No, unless of course the clock you use has extremely high jitter or very low accuracy. But this is unlikely [quote userid="190215" url="~/support/data-converters-group/data-converters/f/data-converters-forum/1472937/ads131m08-question-about-sclk-synchronization-to-master-clock"]What connection of the master clock and SCLK is the best to get higher conversion accuracy?[/quote] This questions is answered by my responses in the other two questions -Bryan
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