Hi Michael Kruger, Thanks for clarifying There is no clear reason why the ADC would read back the same data, unless of course the conversion didn't actually restart (though this is inconsistent with the DRDY behavior) Can you probe the DRDY pin to see if this pin follows the same behavior as the DRDY bit in CONFIG2? Can you try controlling conversions with the START pin instead of the START command to see if that changes the behavior? What SCLK and CLK speeds are you are using? I assume START is tied low, and RESET/PWDN are pulled high? Is the next read after the duplicate always new data? You said this can happen "a few times in a row", so does that mean you can read the same value more than one additional time? Can you be more explicit about how often (does every read get repeated, just certain ones?) and how many repeated data there are? Can you reproduce this issue on your end? It seems like you have gotten systems back from the field that have this issue, but have you had any luck reproducing it on a known good system in your lab for example? Does this issue happen randomly, or is there any discernible pattern to it? An alternative solution to this issue would be to just ignore identical data points during this stabilization period i.e. any time the difference = 0, something is wrong -Bryan
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