Hi Michael Kruger, Thanks, this finally worked. To clarify, in all images, the blue/purple signal is DIN (to the ADC) and the yellow/green signal is DOUT (from the ADC), correct? If I read all of the images left to right, top to bottom, this is what I see. Please address any comments I have made: Send the START command RREG for CONFIG2, DRDY is high, int CLK, SYNCOUT disabled, Pulse control mode RREG for CONFIG2, DRDY is low, int CLK, SYNCOUT disabled, Pulse control mode ?? There is no valid command 0x32 - are you sure you are launching/capturing data on the right SCLK edge? DIN is latched into the ADC on the falling SCLK edge RREG for CONFIG2, DRDY is low , int CLK, SYNCOUT disabled, Pulse control mode --> RDATA command, data = 0x3FE77F, checksum = 0x20 Wait for >3ms, then issue another START command RREG for CONFIG2, DRDY is high, ext CLK, SYNCOUT disabled, Gate control mode --> why is the clock now external, and you are in gate control mode? RREG for CONFIG2, DRDY is high, int CLK, SYNCOUT disabled, Pulse control mode RREG for CONFIG2, DRDY is high, ext CLK, SYNCOUT disabled, Pulse control mode --> why is the clock external again? RREG for CONFIG2, DRDY is low , int CLK, SYNCOUT disabled, Pulse control mode --> RDATA command, data = 0x3FE77F, checksum = 0x20 It seems like there is something messed up in your communication, because the settings seem to be changing without you actually doing anything (unless you are performing additional actions and just not capturing them here). Also, the checksum I calculate for 0x3FE77F is 0x40, not 0x20 Please make sure your controller is sending the data to DIN on the appropriate SCLK edge, and that your analyzer is capturing data from DOUT on the appropriate SCLK edge -Bryan
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