Hi Amit, We could simulate successfully. A mismatch in frequencies of sysref, ref_clk and free-running DRP clk (displayed by default in xcvr wizard) was causing eof and eomf errors in simulations. e.g. at 5 Gbps, ref_clk input freq of 62.5 Mhz would not give these errors unlike with ref_clk = 125 Mhz. We are facing the challenges in on board testing. The external loopback is giving eomf errors now. Please find the .xci file attached. The Trx IP was upgraded. Line rate = 10 Gbps, PLL Type QPLL0, Actual reference clock=125 Mhz. Sysclk= 125 Mhz. We are receiving the data but see eomf error count max out to 'f'. cfg_rx_buffer_release_delay was set to 0. Hope to get some solution for this issue.
↧