Hello Cameron, ADS127L21 is typically used in continuous conversion mode (START/STOP mode). In this case, once the START pin is set high and held there, the ADS127L21 will continuously convert data and toggle the /DRDY pin at the data rate, with a falling edge on DRDY indicating when new conversion data are ready to be read by the host processor. Regarding your question, no, the FPGA only needs to send a single START rising edge to synchronize all ADCs when using START/STOP mode. In order to synchronize multiple ADS127L21's, all ADCs should use the same clock and a common START rising edge will then synchronize all ADCs. For more details regarding synchronization, please take a look at this application note. https://www.ti.com/lit/pdf/sbaa520 Regards, Keith Nicholas Precision ADC Applications
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