Forum Post: RE: TI-JESD204-IP: Help Needed: Errors in Vivado While Generating Bit File for TI JESD204C IP Core on Xilinx FPGA

Hi Akash, Kindly follow the exact steps as per the documentation. You seem to be using the file that is encrypted for QuestaSim. The first error that you have listed indicates that the tool wasn't able to decrypt the RTL. Regards, Ameet