Part Number: TI-JESD204-IP Tool/software: Hi All, There is a bit of problem when trying to add the JESD204C IP core (TI_204c_IP) on the current version of Vivado 2023.1 for the ZC706 board. I've added the IP to my design, but I'm getting the following errors during the implementation phase: DRC. Opt_design not run. e2e.ti.com/.../impl_5F00_log.txt below is the error Synthesis synth_1 [Constraints 18-1056] Clock 'fpga_ref_clk' completely overrides clock 'sys_clk_p'. New: create_clock -period 8.138 -name fpga_ref_clk [get_ports sys_clk_p], ["C:/Users/user/Downloads/project_9/project_9.srcs/constrs_1/imports/DesignFiles/constraints.xdc": and 2] Previous: create_clock -period 8.138 [get_ports sys_clk_p], ["c:/Users/user/Downloads/project_9/project_9.gen/sources_1/ip/sys_pll/sys_pll/sys_pll_in_context.xdc": and 1] [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_pins TI_IP_inst/mgt_rx_usrclk2]]'. ["C:/Users/user/Downloads/project_9/project_9.srcs/constrs_1/imports/DesignFiles/constraints.xdc":9] Implementation Design Initialization [Constraints 18-1055] Clock 'fpga_ref_clk' completely overrides clock 'sys_clk_p', which is referenced by one or more other constraints. Any constraints that refer to the overridden clock will be ignored. New: create_clock -period 8.138 -name fpga_ref_clk [get_ports sys_clk_p], ["C:/Users/user/Downloads/project_9/project_9.srcs/constrs_1/imports/DesignFiles/constraints.xdc": and 2] Previous: create_clock -period 8.138 [get_ports sys_clk_p], ["c:/Users/user/Downloads/project_9/project_9.gen/sources_1/ip/sys_pll/sys_pll.xdc": and 56] [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks -of_objects [get_pins TI_IP_inst/mgt_rx_usrclk2]]'. ["C:/Users/user/Downloads/project_9/project_9.srcs/constrs_1/imports/DesignFiles/constraints.xdc":9] [Vivado 12-5201] set_clock_groups: cannot set the clock group when only one non-empty group remains. ["C:/Users/user/Downloads/project_9/project_9.srcs/constrs_1/imports/DesignFiles/constraints.xdc":9] [Project 1-486] Could not resolve non-primitive black box cell 'TI_204c_IP' instantiated as 'TI_IP_inst' ["C:/Users/user/Downloads/project_9/project_9.srcs/sources_1/imports/rtl/TI_204c_IP_ref.sv":520] Opt Design DRC Netlist Design Level [DRC INBB-3] Black Box Instances: Cell 'TI_IP_inst' of type 'TI_204c_IP' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run. There is a problem where Vivado doesn’t seem to know the definition of the IP core and is treating it as a black box. But if you look down it shows that the IP core is included in my project and all the necessary files are derived. Is anyone else familiar with this problem? Feedback on better ways of solving this would be highly welcome. Thanks and regards balu
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