Part Number: ADC3444EVM Other Parts Discussed in Thread: ADC3444 Tool/software: Hello, We are using the ADC3444 with the ZCU102, and the RTL work was completed in Xilinx Vivado 2018.3. We have implemented and successfully simulated the RTL code, which is functioning as expected. We are generating all clocks based on the DCLK. However, when operating the ADC at 100 MSPS and testing with a ramp test pattern, we observe that some bits toggle incorrectly for a small number of clocks—typically within a single frame clock.Due to this we observe glitches in ramp output. But if we use 90 msps sampling rate then ramp data is continous without any bit glitches.This is one issue we are encountering. The second issue arises when we use 125msps sampling rate. We also change the respective clock rates in the MMCM when we change sampling rate. While testing with the ramp pattern at 125 sampling rate, we notice that successive samples differ by a value of 4. We are uncertain if this discrepancy is due to the pattern generation at this sampling rate or if there is sample loss occurring. Notably, this issue does not manifest at the 100 MSPS sampling rate. These 2 issues are observed in all the channels. Your assistance in diagnosing these issues would be greatly appreciated. Best regards.
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