Hi Jon, Glad to hear you are able to program now. These warnings typically occur when the FPGA design does not detect a DCLK from the ADC. There are a few things that could be causing this. The DCLK is genrated by the ADC from the sample clock. Assuming you are providing a 65MHz clock signal (since you are using the ADC3910D065) to the SMA connector on the EVM labeled CLK, ensure the clock amplitude is sufficient, around 10dB. You also need to ensure that you program the ADC by running the ADC3910D125EVM_API_Rev0.1.py python script provided in the software package. The ADC will not output a DCLK until it has been programmed using this script. Therefore, you must provide a CLK, run the script to program the ADC, then program the FPGA in that order. This sequence should allow you to program the FPGA and capture data. If you are still recieving errors, please let me know and we can set up a call to debug your setup. Best, Luke
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