Hi Luke, I was able to figure out that the USB and Digilent JTAG pod were conflicting. So I was able to program by removing the USB. Now however, when I program the FPGA using the supplied 10b_DDR.bit and .ltx files I get the following errors.: WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped. WARNING: [Xicom 50-38] xicom: No CseXsdb register file specified for CseXsdb slave type: 0, cse driver version: 0. Slave initialization skipped. INFO: [Labtools 27-1434] Device xc7a100t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3361] The debug hub core was not detected. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active. 2. Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'. For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908). WARNING: [Labtools 27-3413] Dropping logic core with cellname:'design_1_i/DCLK_ILA' at location 'uuid_9E5F81CB5AFE5EBD9B083A60DFA7040F' from probes file, since it cannot be found on the programmed device. WARNING: [Labtools 27-3413] Dropping logic core with cellname:'design_1_i/DCLKz_ILA' at location 'uuid_D4760B86CACE5B4A85361056704FD62B' from probes file, since it cannot be found on the programmed device.
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