Mr Hegde -
The SPI mode, the DRDY pulse will occur at the data rate frequency (see Figure 76).
As for the calculation of OSR and fdata , please refer to the Tables mentioned in the previous post. Table 3 shows the fmod to fdata relationship and Table 6 shows the fclk to fmod relationship. This gets you the results shown at the end of your statement highlighted in red.
fmod is the modulator clock of the data converter; since this is a delta sigma or oversampling converter this is higher than the actual data rate.
fdata is the actual data rate the will be output from the ADC. The relationship to the fmod is called the over-sampling ratio (OSR). (see Table 3)
fclk is the master clock frequency to the ADC (can be provided internally or externally).
You may want to further review delta-sigma ADC operation for further details on how they operate versus SAR ADCs.