Hi Ryan
Can you provide the full sequence of data you are seeing in the 2 cases you describe? Looking at only 5 data points doesn't show the full test pattern sequence. For non-demux mode we need to see at least 6 samples from the I output channel. For the 1:2 demux case in the reference board we need to look at 11 or more data points. (Id and I data is interleaved together in the reference board GUI software). For the reference board the full sequence in 1:2 demux will be:
I channels, Id and I combined: FEFh, 010h, FEFh, 010h, 010h, FEFh, 010h, FEFh, 010h, 010h, FEFh, 010h, ..... (Bold highlight on first sample of pattern)
Regarding what you see with your ADC12D500RF board, when switching between non-demux and 1:2 demux mode, please remember that the ADC12D500RF device may also change the DCLK clocking mode. Non-demux mode can operate with DDR or SDR output clocking, while 1:2 demux mode only allows SDR output clocking. What may be occuring is that when you switch to 1:2 demux mode via pin control the FPGA is still capturing using DDR clocking, and is therefore grabbing each data sample twice.
Regarding the ADC12D800RFRB behavior, as you have seen, the reference board only supports 1:2 demux mode data capture. Even if the ADC itself is configured as non-demux mode the FPGA expects to receive 1:2 demux data outputs.
One shortcoming of the Test Pattern Mode data of this particular device (ADC12D500RF/ADC12D800RF) is that the patterns are somewhat ambiguous between the Non-Demux and Demux modes. Depending on how data is captured, both modes look similar.
Please let us know what the full test patterns you are capturing look like, and how your FPGA is capturing the data.
Hopefully this information is helpful.
Best regards,
Jim B