Hi Pedro,
The R4 and R5 resistor pack are 33ohm series resistors, which is useful for damping out ringing in the rise/fall transitions in the data line. You can find the part # in the BOM section of the EVM user's guide: http://www.ti.com/lit/ug/slau032c/slau032c.pdf
The clock input of the THS5651a is designed to accept CMOS level input. You may refer to page 6 of the datasheet for VIh and Vil requirements of the CMOS clock input (http://www.ti.com/lit/ds/slas197a/slas197a.pdf).
There should be a lot of CMOS buffer with sufficient slew rate that could work fine. The SN74LVC2G07DBVR that you mentioned is open drain output, which means that you will need to tie pull-up resistors to the output for the part to function. You may select the part from the TI web:
http://www.ti.com/lsds/ti/logic/ll-buffer-gate-products.page?paramCriteria=no
The following part may be a good starting point. You can see that the Voh and Vol of the part have wider range than the input spec of the THS5651a.
http://www.ti.com/lit/ds/symlink/sn74lvc1g126.pdf
In general, we do not recommend clocking the data converters with FPGA due to the high jitter content. You may want to clock the THS5651a with clock drivers such as CDCE62005 or LMK04800 family.
-Kang