Hi Abel,
It looks like the CH1 vertical scale is set to 1 V/div and the SCLK signal doesn't span an entire division. Meanwhile your schematic, SDIN, and CS show ~5V logic. Why does the SCLK look to be attenuated?
Hi Abel,
It looks like the CH1 vertical scale is set to 1 V/div and the SCLK signal doesn't span an entire division. Meanwhile your schematic, SDIN, and CS show ~5V logic. Why does the SCLK look to be attenuated?