Hi Rob,
You're welcome! Debug is always fun; I hope your system works as designed.
When is the clock applied to the ADC, relative to the power? The power rails (VA, VTC, VENC, etc.) should come up first. This might be messing up the control registers. I have seen it happen before - if the clock is applied before power, then the ESD diodes activate and dump the power into the rails. Since they are powered up a bit, some unpredictable content can get programmed into the control registers.
To check whether the POR is happening properly, you can set the ADC into Non-ECM and back again. You can do this by setting ECEb high - and then low again. Upon entering ECM, the control registers should be set to their defaults again. So try the following:
1. Power your system up and read the registers. If you read FFFFh on Reg 8h, then your bug is still there.
2. Cycle ECEb HI then LO again. Read the registers again. If you read 000h, then at least the POR feature is working.
Another detail... you mention that the power rails are 1V8, but for the ADC, all rails should be 1V9. Can you confirm the power supply?
Is this your first design with the ADC12D1600? If you want to double-check for a board spin, we are happy to do a schematics / layout review of the ADC, clock drive, and analog input. Please just allow 1 week for review.
Register 8h is labeled as 'Reserved' in the datasheet. It does have some internal test purposes, so it would be best that it is at the recommended default value as you evaluate.
Kind regards,
Marjorie