Part Number: ADC12DJ3200 Hello... I am using a COTS board and it uses the ADC12DJ3200 . I am always using it in the “dual-channel mode” and I’m always sampling at 1333.333 MHz. I am always running in the 2 nd Nyquist zone, so my analog BW is from 750 – 1250 MHz. I do not need any of the DDCs or internal processing of the ADC12DJ3200 ; I just need straight time-domain data. In this application, I need the largest possible SFDR within my analog BW. It doesn't matter to this application if the spurs are harmonics, or clock related, or at fixed frequencies. Based on dBc, I need to knock down whatever becomes the highest spur . Since I’m sampling the ADC at a rate that’s much slower than its maximum, I have a question: 1) Are there internal registers that may need to be tweaked for this specific sample rate in order to maximize SFDR? I am working with the COTS vendor to learn how they are programming those registers, but I’d appreciate any insights you can provide. Thanks...
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