Part Number: LM98640QML-SP Hi, The datasheet provides LVDS timing specifications at an INCLK frequency of 40 MHz. Do you have any data at other INCLK frequencies? I would expect the timing requirements to be relaxed at lower frequencies. Is that correct? Do you have any specifications? Also, can I assume that the LVDS output clock (TXCLK) is 50% duty cycle? I don't see that explicitly stated anywhere. If so, is that guaranteed? In quad lane mode, it figures into calculations for the falling edge setup time and the rising edge hold time. Thanks, Bradley
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