Greg,
The problem is solved. The CS\ pin needs at low level in all the initialization and RDATAC period.
Yes, the hardware Start pin is tied to low.
Your comments are helpful and thank you.
I have following findings, suggestions and questions for the data sheet:
1. In the Fig50, it is better to mention to set CS\ pin at low after Set PWDN\ and RESET\=1.
2. In Settling Time section (page 28), it mentions the Table 5. But Table 5 is nothing related to settling time.
3. In Settling Time section, it states "Settled data are available on the fourth DRDY pulse.". What does this mean? What is this referred to (which is the first DRDY in the Fig33?)
4. In page 35, "Assuming SCLK is 2.048 MHz", it should be "Assuming CLK is 2.048 MHz,".
5. In page 43, for FAULT_STATP and FAULT_STATN registers, those fault bits will be set to ONE when the faults occur? Please confirm it.
6. In your last post, you suggested to send Start command after the RDATAC command. This is good way. But in the data sheet page 34, it states "If the device is in RDATAC mode, an SDATAC command must be issued before any other commands can be sent to the device". This statement is conflicted to what your suggestion.
7. In RDATAC mode with 24bit conversion, 24bit x 8ch+24bit=216bit, if MCU sends total 14 x 16bit=224 SCLKs, 8bit more than needed for data read, this will make any problem for the ADC?
Thank you for help,
Ming