Hi Joffray
The time offset you are observing is due to a bug in that version of the FPGA firmware on the reference board. The I and Q data FIFOs are not properly synchronized during capture and readout.
Here is what I see before that change is made, operating in non-DES I and Q mode:
You can verify this by changing the operating mode to DESI in the Wavevision 5 GUI,
and then forcing the ADC mode back to non-DES by making the setting of Register 0x000, Bit 7 = 0 via the Debug 0 Register interface.
Here is what I see after these changes:
This configuration will make the FPGA handle the data as if the ADC is in DES mode so the FIFOs are set up and synchronized properly. The data will all be captured into a common buffer but can then be de-interleaved in your matlab code.
I don't have it available at the moment, but I will work to get an updated FPGA firmware image posted here that resolves this issue for this board. We will also incorporate the updated firmware image into a future revision of the Wavevision 5 software download.
I hope this is helpful.
Best regards,
Jim B