Hi,Alex,
I believe you have already had a good unstanding about the clock in our Codec. very good!
1.If you use different sampling rates for the ADC and the DAC, you must also use two separate Frame Sync (=WCLK) signals, one for the ADC and one for the DAC. If you use the same FS (WCLK) for both the ADC and DAC then both will effectively convert at the same rate because you'll feed/read data at the same sample rate.
2.AIC3100 has Primary and Secondary Audio Interface,so that you can configure WCLK out = DAC_FS and GPIO 1= ADC_FS. Check page 78.
3.The bit clock can be shared by both ADC and DAC but it must be running fast enough to allow for the faster sampling rate(32khz).
Thanks,
Flora Wang