Forum Post: RE: AFE7222 / about AUX DAC, 8-sample FIFO mode and LVDS threshold voltage

Hi Ryuji,

1) LVDS threshold voltages for AFE7222 is +100mV (for logic high) and -100mV (for logic low). The +/-350mV is just the LVDS standard voltage swing

2) Yes, in direct access mode, SCLK needs to keep running and SEN has to be low. Data is loaded into the DAC using the SPI interface

3) Based on the AUX DAC ADDR [11:6]=010001 both AUX_DAC_A and AUX_DAC_B are being used so 0x20A [1:0] needs to be set to 11

4) In 8-sample FIFO mode, DCLKIN is still needed to ensure correct operation of the transmit FIFOs

Thanks,

Eben.