Hi Fabio,
DRDY signals when new conversion results are available. This is a transition from high to low. If you do not read the results between conversion periods, you will see that DRDY remains low, and a pulse will occur that signals the end of conversion and an update period of the new data results to the results register. What you are seeing is normal behavior. If you send an SCLK between conversions you will see that DRDY goes high as you expect. In this case you will not see the pulse, just the transition from high to low.
I do have one suggestion. It appears that you are leaving MISO and MOSI float. I would suggest using a weak pull-up on these lines using 100k ohm resistors so that the CMOS inputs are not floating. This eliminates the potential for the input gate from inadvertantly drawing excessive current.
Best regards,
Bob B