Forum Post: RE: DAC8581 tUPDAC timing

     Thanks so much for your (and Eugenio's) help--very illuminating.

     I have attached a partial schematic, but it may not tell you much by itself.  The board is intended for one product as-is, with additional circuitry to validate the DAC8581 at its highest practical sample rate.  It has digital power and ground planes plus an analog ground plane.  There is also a layer to distribute the various other supply and reference voltages.

     There are two DAC8581s.  The first one (in the schematic), and another with its output connected only to test points.  Both get their data from a Microchip dsPIC33EP.

     Logic in a CPLD stretches the dsPIC's Frame Synch pulse so that it can be used as the DAC's CSn.  This is so the DAC can be fed from a block of DMA RAM, minimizing processor overhead.

     The 1st DAC's output is scaled to +/-2.5V quasi-differential to drive a voice-coil servo controller.  500ksps is sufficient for that function.

     The 2nd DAC is for experimentation.  I'm hoping to clock it at 50MHz, transmitting 3 bytes per sample.  The first 2 bytes are the sample data.  The 3rd is not clocked into the DAC and its transmission time covers tTD, tWAIT, and then some.  An anti-imaging filter will come later.  The hope is to add a dual purpose programmable voltage output and low-cost arbitrary waveform generator feature to a future product.

     I guess the most important parameter is INL for the first DAC, which is adequate based on the DAC8581's spec sheet.  For the second DAC, sample rate is most important--though more bottom-up.  At this price, we'll take whatever we can reliably get from the part.

Thanks again, Mark