MCLK=SCKI. Same thing. I just used a more common term for the same thing. If the master clock is the same between the PCM1804s and the reset timing is the same, they will run in sync.
>If the sampling timing of SlaveMode is a ramp(or fall) time of LRCK, they can be convinced, but is it right?
You need to synchronize the parts with the same master clock (SCKI) because this is what drives the part internally. This is an oversampling converter meaning it samples at a much higher rate than the sampling rate. For example, if you choose single rate and you want to use a 48kHz sampling rate in slave mode, the oversampling rate is either 256, 384, 512 or 768, depending on the applied master clock(SCKI). So the part samples the input at the resulting oversampling frequency of either 12.288 MHz, 18.432 MHz, 24.576 MHz or 36.864 MHz. The exact phase of the LRCK in slave mode is not critical and will not affect the "sampling timing of SlaveMode" as you wrote in your question. You must make sure that the host supplies the LRCK at the correct rate but the actual sampling is timed by SCKI.
You should also use the same word clock (LRCK) and ideally the same bit clock (BCK) for all PCM1804s.